MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 194

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MC68EC040FE25A

Manufacturer Part Number
MC68EC040FE25A
Description
IC MPU 32BIT 25MHZ 184-CQFP
Manufacturer
Freescale Semiconductor
Series
M68000r
Datasheets

Specifications of MC68EC040FE25A

Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
184-CQFP
Core Size
32bit
Program Memory Size
8KB
Cpu Speed
25MHz
Digital Ic Case Style
CQFP
No. Of Pins
184
Supply Voltage Range
4.75V To 5.25V
Operating Temperature Range
0°C To
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
184
Package Type
CQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68EC040FE25A
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68EC040FE25A
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
7.8.2 Bus Arbitration Examples
The following paragraphs illustrate the behavior of the M68040 bus arbitration scheme
and provide examples of how an external bus arbiter can be designed to keep the integrity
of locked bus operations. The examples include the previously mentioned indeterminate
and disregard request conditions.
7.8.2.1 DUAL M68040 FAIRNESS ARBITRATION. The following state diagram illustrates
a fairness algorithm using two MC68040s and assigning the least priority to the processor
that owns the bus. If both processors keep their respective BR signals asserted, bus
ownership alternates between the two processors so that each processor can run at least
one bus cycle during its tenure. Each processor is allowed to own the bus without
relinquishing it to maintain the integrity of locked transfers. This example also illustrates
7-52
ATTRIBUTES
*
AM indicates the alternate bus master.
TRANSFER
AM_BG
AM_BR
D31–D0
A31–A0
BCLK
Figure 7-34. Implicit Bus Ownership Arbitration Timing
TIP
BR
BG
TA
BB
TS
*
*
Undefined
C1
ALTERNATE
MASTER
Freescale Semiconductor, Inc.
For More Information On This Product,
C2
M68040 USER’S MANUAL
Go to: www.freescale.com
C3
C4
IMPLICITLY
OWNED
BUS
C5
C6
BUS OWNED
AND ACTIVE
PROCESSOR
C7
C8
BUS OWNED
AND IDLE
C9
MOTOROLA

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