MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 290

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

9-46
CMDREG1B
FPTEMP
STAG
E1
T
CMDREG1B
FPTEMP
STAG
E1
T
CMDREG3B
WBTEMP
WBTE15
WBTM1, WBTM0,
SBIT
E3
T
CMDREG1B
FPTEMP
STAG
E1
T
CMDREG1B
ETEMP
STAG
FPTEMP
E1
T
FSAVE State
Frame Field
Table 9-16. State Frame Field Information (Continued)
FMOVE instruction command word
Intermediate result with mantissa rounded to correct precision.
Source Operand Tag = Normalized
Always 1
Always 1
Exception Instruction Command Word
Unrounded, Extended-Precision Intermediate Result
Source Operand Tag = Normalized
Always 1
Always 0
Encoded Exception Instruction Command Word
WBTS, WBTE, and WBTM = intermediate result sign, biased 15-bit
exponent, and 64-bit mantissa prior to rounding.
Bit 15 of the intermediate result's 16-bit exponent = 1 for underflow.
Guard, round, and sticky of intermediate result’s 67-bit mantissa.
Always 1
Either 1 or 0
FMOVE Instruction Command Word
Intermediate result with mantissa prior to rounding.
Source Operand Tag = Normalized
Always 1
Always 1
M68040FPSP divide by zero can generate.
Source operand is converted to extended precision.
Source Operand Tag
Destination operand is converted to extended precision.
Always 1
Always 0
Freescale Semiconductor, Inc.
UNFL (FADD, FSUB, FMUL, FDIV, and FSQRT)
For More Information On This Product,
UNFL (FMOVE to Register, FABS, and FNEG)
M68040 USER’S MANUAL
Go to: www.freescale.com
OVFL (FMOVE to Memory)
UNFL (FMOVE to Memory)
DZ
Contents
MOTOROLA