MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 48

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

procedure separates task-related supervisor activity from asynchronous, I/O-related
supervisor tasks that can only be coincidental to the currently executing task. The MSP
can separately maintain task control information for each currently executing user task,
and the software updates the MSP when a task switch is performed, providing an efficient
means for transferring task-related stack items. The value of the M-bit does not affect
execution of privileged instructions. Instructions that affect the M-bit are MOVE to SR,
ANDI to SR, EORI to SR, ORI to SR, and RTE. The processor automatically saves the M-
bit value and clears it in the SR as part of the exception processing for interrupts.
2.2.2.2 STATUS REGISTER. The SR (see Figure 2-5) stores the processor status. In the
supervisor mode, software can access the full SR, including the CCR available in user
mode (see 2.2.1.5 Condition Code Register) and the interrupt priority mask and
additional control bits available only in the supervisor mode. These bits indicate the
following states for the processor: one of two trace modes (T1, T0), supervisor or user
mode (S), and master or interrupt mode (M).
The term SSP refers to the ISP and MSP. The M and S bits of the SR decide which SSP
to use. When the S-bit is one and the M-bit is zero, the ISP is the active stack pointer;
when the S-bit is one and the M-bit is one, the MSP is the active stack pointer. The ISP is
the default mode after reset and corresponds to the MC68000, MC68008, MC68010, and
CPU32 supervisor mode.
2.2.2.3 VECTOR BASE REGISTER. The VBR contains the base address of the exception
vector table in memory. The displacement of an exception vector is added to the value in
this register to access the vector table. Refer to Section 8 Exception Processing for
information on exception vectors.
2.2.2.4 ALTERNATE FUNCTION CODE REGISTERS. The alternate function code
registers contain 3-bit function codes. Function codes can be considered extensions of the
32-bit logical address that optionally provides as many as eight 4-Gbyte address spaces.
The processor automatically generates function codes to select address spaces for data
and programs at the user and supervisor modes. Certain instructions use the SFC and
DFC registers to specify the function codes for operations.
MOTOROLA
MASTER/INTERRUPT STATE
SUPERVISOR/USER STATE
15
T1
ENABLE
TRACE
14
T0
Freescale Semiconductor, Inc.
13
S
For More Information On This Product,
SYSTEM BYTE
12
M
Figure 2-5. Status Register
11
0
Go to: www.freescale.com
M68040 USER’S MANUAL
10
I2
PRIORITY MASK
INTERRUPT
9
I1
I0
8
7
0
6
0
(CONDITION CODE REGISTER)
5
0
USER BYTE
4
X
3
N
2
Z
1
V
0
C
CARRY
OVERFLOW
ZERO
NEGATIVE
EXTEND
2- 7