MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 386

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

B.5.2 MC68EC040 Stack Frames
When the processor executes an RTE instruction, it examines the stack frame on top of the
active supervisor stack to determine if it is a valid frame and what type of context restoration
it requires. The set of stack frames included for exception processing are four- and six-word
stack frames, a four-word throwaway stack frame, an access error stack frame, and a new
eight-word unimplemented floating-point stack frame. The stack frame that the MC68040
can generate and the MC68EC040 can process is the floating-point post-instruction stack
frame. Refer to Section 8 Exception Processing for details about exception stack frames.
When the MC68EC040 writes or reads a stack frame, it uses long-word operand transfers
wherever possible. Using a long-word-aligned stack pointer greatly enhances exception pro-
cessing performance. The processor does not necessarily read or write the stack frame data
in sequential order. The system software should not depend on a particular exception gen-
erating a particular stack frame. For compatibility with future devices, the software should be
able to handle any type of stack frame for any type of exception. The MC68EC040 does not
generate the floating-point post-instruction stack frame. The MC68040 cannot accept the
eight-word unimplemented stack frame. The MC68EC040 can handle all MC68040 stack
frame formats.
B.6 SOFTWARE CONSIDERATIONS
The following MC68EC040 instructions are different from the MC68040: PTEST, PFLUSH,
CPUSH, CINV, MOVEC, and all floating-point instructions.
B-10
MC68EC040
SP
+$0C
+$02
+$06
+$08
direct addressing modes, this field is $0. The saved PC value is the logical address of
the instruction that follows the unimplemented floating-point instruction. This value will
be restored during RTE execution. The vector offset format number ($4) is used for
this eight-word stack frame. Note that an MC68040 cannot correctly handle a stack for-
mat $4. The PC of the faulted instruction contains a long-word PC of the floating-point
instruction that caused the trap to occur. The information is provided so that the in-
struction is available for software emulation of floating-point instructions. The proces-
sor generates exception vector number 11 for the unimplemented F-line instruction
exception vector, fetches the address of the F-line exception handler from the excep-
tion vector table, and begins execution of the handler after prefetching instructions to
fill the pipeline. Refer to Section 8 Exception Processing for details about exception
processing.
15
0100
REV2.3 (01/31/2000)
EFFECTIVE ADDRESS
PROGRAM COUNTER
Stack Frames
STATUS REGISTER
PC OF FAULTED
INSTRUCTION
VECTOR OFFSET
Freescale Semiconductor, Inc.
For More Information On This Product,
Eight-Word Stack Frame (Format $4)
Go to: www.freescale.com
M68040 USER’S MANUAL
0
The MC68040 cannot
generate or read this stack.
Exception Types
Effective address field is
the address of the faulted
instruction operand.
Stacked PC Points To
MOTOROLA