MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 214

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

SECTION 8
EXCEPTION PROCESSING
Exception processing is the activity performed by the processor in preparing to execute a
special routine for any condition that causes an exception. In particular, exception
processing does not include execution of the routine itself. This section describes the
processing for each type of integer unit exception, exception priorities, the return from an
exception, and bus fault recovery. This section also describes the formats of the exception
stack frames. For details on floating-point exceptions refer to Section 9 Floating-Point
Unit (MC68040 Only).
8.1 EXCEPTION PROCESSING OVERVIEW
Exception processing is the transition from the normal processing of a program to the
processing required for any special internal or external condition that preempts normal
processing. External conditions that cause exceptions are interrupts from external
devices, bus errors, and resets. Internal conditions that cause exceptions are instructions,
address errors, and tracing. For example, the TRAP, TRAPcc, FTRAPcc, CHK, RTE, DIV,
and FDIV instructions can generate exceptions as part of their normal execution. In
addition, illegal instructions, unimplemented floating-point instructions and data types, and
privilege violations cause exceptions. Exception processing uses an exception vector
table and an exception stack frame. The following paragraphs describe the vector table
and a generalized exception stack frame.
The M68040 uses a restart exception processing model to minimize interrupt and
instruction latency and to reduce the size of the stack frame (compared to the frame
required for a continuation model). Exceptions are recognized at each instruction
boundary in the execute stage of the integer pipeline and force later instructions that have
not yet reached the execute stage to be aborted. Instructions that cannot be interrupted,
MOTOROLA
For the MC68040V, MC68LC040, MC68EC040, and
MC68EC040V ignore all references to floating-point, including
any instructions that begin with an “F”. Also, for the
MC68EC040 and MC68EC040V ignore all references to the
memory management unit (MMU) and the instructions
PFLUSH and PTEST. The functionality of the MC68040
transparent translation register has been changed in the
MC68EC040 and MC68EC040V to the access control registers
(ACR). Refer to Appendix A MC68LC040 and Appendix B
MC68EC040 for details.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
M68040 USER’S MANUAL
NOTE
8- 1