MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 265

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

exception and the F-line illegal instruction share the same vector, the exception handler
uses the stack frame format ($0 or $2) to distinguish between the two.
When an unimplemented floating-point instruction is encountered, the processor waits for
all previous floating-point instructions to complete execution. Pending exceptions are
taken and handled prior to the execution of the unimplemented instruction.
Next, the instruction is partially decoded to allow fetching of the memory source operand,
if required. When the operand fetch begins, all other read accesses for previous
instructions are complete, and only the execution and write-back of results for previous
integer instructions remains to be completed. If an access error (bus error) occurs in
fetching the operand or in completing any other access before beginning the operand
fetch, the unimplemented instruction is restarted after the processor returns from
exception handling for the error. Refer to Section 8 Exception Processing for more
information on access errors.
The fetched source operand is passed to the FPU, which converts the operand to
extended precision and saves the intermediate result. If the operand is an unsupported
data type (denormalized, unnormalized, or packed decimal real), the unimplemented
floating-point exception takes precedence, and the floating-point instruction emulation
routine must detect the unsupported data type.
The processor begins exception processing for the unimplemented floating-point
instruction by making an internal copy of the current SR. The processor then enters the
supervisor mode and clears the trace bits (T1, T0). The processor creates a format $2
stack frame and saves the vector offset, PC, internal copy of the SR, and calculated
MOTOROLA
Freescale Semiconductor, Inc.
Table 9-10. Unimplemented Instructions
For More Information On This Product,
FTWOTOX
FGETMAN
FETOXM1
FGETEXP
FATANH
FSCALE
FACOS
FCOSH
FATAN
FETOX
FASIN
FCOS
FMOD
FINT
Go to: www.freescale.com
M68040 USER’S MANUAL
Monadic Operations
Dyadic Operations
FMOVECR
FLOGNP1
FTENTOX
FSINCOS
FLOG10
FINTRZ
FLOGN
FTANH
FSINH
FREM
FTAN
FSIN
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