MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 40

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MC68EC040FE25A

Manufacturer Part Number
MC68EC040FE25A
Description
IC MPU 32BIT 25MHZ 184-CQFP
Manufacturer
Freescale Semiconductor
Series
M68000r
Datasheets

Specifications of MC68EC040FE25A

Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
184-CQFP
Core Size
32bit
Program Memory Size
8KB
Cpu Speed
25MHz
Digital Ic Case Style
CQFP
No. Of Pins
184
Supply Voltage Range
4.75V To 5.25V
Operating Temperature Range
0°C To
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
184
Package Type
CQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68EC040FE25A
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68EC040FE25A
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
MOTOROLA
ROXL, ROXR
ORI to CCR
ROL, ROR
ORI to SR
PFLUSH 8
Opcode
PTEST 8
RESET
PACK
SBCD
STOP
NOP
NOT
SUB
PEA
RTD
RTE
RTR
RTS
ORI
Scc
OR
None
~ Destination ø Destination
Source V Destination ø Destination
Immediate Data V Destination ø Destination
Source V CCR ø CCR
If supervisor state
else TRAP
Source (Unpacked BCD) + adjustment ø
SP – 4 ø SP; <ea> ø (SP)
If supervisor state
else TRAP
If supervisor state
else TRAP
If supervisor state
else TRAP
Destination Rotated by count ø Destination
Destination Rotated with X by count ø Destination
(SP) ø PC; SP + 4 + d n ø SP
If supervisor state
else TRAP
(SP) ø CCR; SP + 2 ø SP;
(SP) ø PC; SP + 4 ø SP
(SP) ø PC; SP + 4 ø SP
Destination10 – Source 10 – X ø Destination
If condition true
else 0s ø Destination
If supervisor state
else TRAP
Destination – Source ø Destination
then Source V SR ø SR
Destination (Packed BCD)
then invalidate instruction and data ATC entries
for destination address
then logical address status ø MMUSR;
entry ø ATC
then Assert RSTO Line
then (SP) ø SR; SP + 2 ø SP; (SP) ø PC;
SP + 4 ø SP; restore state and deallocate
stack according to (SP)
then 1s ø Destination
then Immediate Data ø SR; STOP
Table 1-4. Instruction Set Summary (Continued)
Freescale Semiconductor, Inc.
For More Information On This Product,
Operation
Go to: www.freescale.com
M68040 USER’S MANUAL
NOP
OR Dn,<ea>
ORI #<data>,CCR
ORI #<data>,SR
PACK –(Ax),–(Ay),#(adjustment)
PACK Dx,Dy,#(adjustment)
PEA <ea>
PFLUSH (An)
PFLUSHN (An)
PFLUSHA
PFLUSHAN
PTESTR (An)
PTESTW (An)
RESET
ROd #<data>,Dy 1
ROXd #<data>,Dy 1
ROXd <ea> 1
RTD #(d n )
RTE
RTR
RTS
SBCD Dx,Dy
SBCD –(Ax),–(Ay)
Scc <ea>
STOP #<data>
SUB Dn,<ea>
NOT <ea>
OR <ea>,Dn
ORI #<data>,<ea>
ROd Rx,Dy 1
ROXd Dx,Dy 1
SUB <ea>,Dn
Syntax
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