MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 279

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The user UNFL exception handler must execute an FSAVE as its first floating-point
instruction. At this point, the destination contains the rounding mode values listed in Table
9-13, and the user UNFL exception handler can choose to modify these values. The E3
and E1 bits of the floating-point state frame need to be examined to determine which fields
on the floating-point state frame are valid. E3 always takes precedence and must always
be serviced first. Table 9-16 lists the floating-point state frame fields for OVFL exceptions
with E3 set or with E3 clear and E1 set. It is possible for an FADD, FSUB, FMUL, and
FDIV to report a post-instruction exception, although these instructions normally generate
a pre-instruction exception. The following example illustrates why a post-instruction
exception is generated.
In this example, assume that the FMOVE instruction starts once the FADD instruction
generates an underflow. Given the register dependency on FP0, the destination of the
FADD instruction, FP0 needs to be resolved prior to the FMOVE instruction execution. For
this example, there is no choice but to have the FADD instruction report a post-instruction
exception immediately. Note that for this case, even though the T-bit of the floating-point
state frame is set (post-instruction exception), it does not imply an FMOVE OUT
instruction. Therefore, the effective address field in the format $3 stack frame is invalid.
The FMOVE OUT instruction generates a post-instruction exception. For this case, the
effective address field in the format $3 stack frame points to the destination memory
location. If the destination is an integer data register, the FPIAR points to the F-line word
of the offending instruction, and the F-line word contains the integer data register number.
If the M68040FPSP unimplemented instruction exception handler is used, there can be
some other cases in which an underflow is reported. If an INEX2 or INEX1 exceptional
condition exists and the user INEX exception handler is enabled, it is the responsibility of
the user UNFL exception handler to look for this situation.
The user UNFL exception handler examines the E3 bit of the floating-point state frame to
exit from this exception handler. If the E3 bit is set, it must be cleared prior to restoring the
floating-point frame through the FRESTORE instruction. If the E3 bit is clear and the E1 bit
MOTOROLA
a. If the user UNFL exception handler is disabled, the M68040FPSP UNFL exception
b. If the user UNFL exception handler is enabled, the M68040FPSP UNFL exception
FADD
FMOVE
handler checks for an INEX1 or INEX2 exception condition with the user INEX
exception handler enabled. If not, the processor returns to normal instruction flow.
Otherwise, the M68040FPSP UNFL exception handler restores the FPU to its
exceptional state, cleans up the stack to the conditions prior to execution, and
continues instruction execution at the user INEX exception handler. No parameters
are passed to the user INEX exception handler since the M68040FPSP UNFL
exception handler provides the illusion that it never existed. Otherwise, the
M68040FPSP UNFL exception handler returns the processor to normal processing.
handler restores the FPU to its exceptional state, cleans up the stack to the
conditions prior to execution, and continues instruction execution at the user UNFL
exception handler. Once the M68040FPSP UNFL exception handler recognizes the
operand error as a maskable condition, it does not modify the destination or pass
control to the user UNFL exception handler.
FP2,FP0
FP0, <ea>
Freescale Semiconductor, Inc.
For More Information On This Product,
; this instruction is executing when underflow occurs
; this instruction generates an underflow exception
Go to: www.freescale.com
M68040 USER’S MANUAL
9- 35