MC68030RC50C Freescale Semiconductor, MC68030RC50C Datasheet - Page 282

• Manufacturer Part Number: MC68030RC50C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC50C

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
t h a n the value in the mask, the processor makes the request a pending
The IPL0-/PL2 interrupt signals must maintain the interrupt request level until
the MC68030 acknowledges the interrupt to guarantee that the interrupt is
these signals. An interrupt request that is the same for two consecutive falling
the request remain until the processor runs an interrupt acknowledge cycle
for that interrupt value, an interrupt request that is held for as short a period
that the processor ignores. When an interrupt request has a priority higher
The peripheral device uses the active-low interrupt priority level signals
the priority of that condition. The three signals encode a value of zero through
seven (IPL0 is the least significant bit). High levels on all three signals cor-
recognized. The MC68030 continuously samples the IPL0-1PL2 signals on
consecutive falling edges of the processor clock to synchronize and debounce
clock edges is considered a valid input. Although the protocol requires that
as two clock cycles could be recognized.
The status register of the MC68030 contains an interrupt priority mask (12,
(IPL0-1PL2) to signal an interrupt condition to the processor and to specify
of prioritized interrupts; level seven has the highest priority. External circuitry
can chain or otherwise merge signals from devices at each level, allowing
an unlimited number of devices to interrupt the processor.
I1, 10, bits 10-8). The value in the interrupt mask is the highest priority level
interrupt. Figure 8-2 is a flowchart of the procedure for making an interrupt
pending.
respond to no interrupt requested (level 0) and low levels on IPL0-1PL2 cor-
respond to interrupt request level 7. Values 1-7 specify one of seven levels
J.j /,ERW,SE 0RTRANSm0
Figure 8-2. Interrupt Pending Procedure
MC68030 USER'S MANUAL
i=
I
I
C
SAMPLE AND SYNCH
ASSERT IPEND
,PL2:IPL0
RESET
I
[
0N' E Vi,' ,
(COMPARE I N TERRUPT LEVEL
I
8-15
8