MC68030RC50C Freescale Semiconductor, MC68030RC50C Datasheet - Page 296

• Manufacturer Part Number: MC68030RC50C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC50C

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

8.2.2 Using Software To Complete the Bus Cycles
MOTOROLA
of the pipe are accepted as valid; the processor assumes that there is no
The least significant half of the SSW applies to data cycles only. If the DF bit
of the SSW is set, a data fault has occurred and caused the exception. If the
data access; otherwise, it assumes that the data input buffer value on the
stack is valid for a read or that the data has been correctly written to memory
for a write (or that no data fault occurred). The RM bit of the SSW identifies
was a read or write operation. The SIZE field indicates the size of the operand
to emulate the cycle. This is the only method for correcting address errors.
The handler should emulate the faulted bus cycle in a manner that is trans-
the handler may need to run bus cycles for both the B and C stages of the
was made to use its contents. Those stages must be repaired. For each faulted
saved on
that it has corrected. The handler should not change the fault bits FB and
prefetch pending for the corresponding stage and that software has repaired
or filled the image of the stage, if necessary.
If an address error exception occurs;the fault bits written to the stack frame
are not set (they are only set due to a bus error, as previously described),
and the rerun bits alone show the cause of the exception. Depending on the
state of the pipeline, either RB and RC are both set, or RC alone is set. To
correct the pipeline contents and continue execution of the suspended in-
struction, software must place the correct instruction stream data in the stage
C and/or stage B images requested by the rerun bits and clear the rerun bits.
DF bit is set when the processor reads the stack frame, it reruns the faulted
a read-modify-write operation and the RW bit indicates whether the cycle
access, and the FC field specifies the address space for the data cycle. Data
and instruction stream faults may be pending simultaneously; the fault han-
dler should be able to recognize any combination of the FC, FB, RC, RB, and
One method of completing a faulted bus cycle is to use a software handler
parent to the instruction that caused the fault. For instruction stream faults,
instruction pipe. The RB and RC bits identify the Stages that may require a
bus cycle; the FB and FC bits indicate that a stage was invalid when an attempt
stage, the software handler should copy the instruction word from the proper
address space as indicated by the S bit of the copy of the status register
In addition, the handler must clear the rerun bit associated with the stage
FC.
DF bits.
the stack to the image of the
MC68030 USER'S MANUAL
appropriate
stage in the stack frame.
8-29