MC68030RC50C Freescale Semiconductor, MC68030RC50C Datasheet - Page 47

• Manufacturer Part Number: MC68030RC50C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC50C

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

2
2-2
2.2 O R G A N I Z A T I O N OF DATA IN REGISTERS
2.2.1 Data Registers
Although many BCD codes have been devised, the BCD instructions of the
of a binary number having the numeric value of the corresponding decimal
M68000 Family support formats in which the four least significant bits consist
number. Two BCD formats are used. In the unpacked BCD format, a byte
the data registers.
Binary-coded decimal (BCD) data represents decimal numbers in binary form.
word operands the low-order 16 bits, and long-word operands the entire 32
as bit zero, and the most significant bit is addressed as bit 31. For bit fields,
the most significant bit is addressed as bit zero, and the least significant bit
the offset is greater than 32, the bit field wraps around within the register.
The following illustration shows the organization of various types of data in
on order or pairing. There are no explicit instructions for the
The eight data registers can store data operands of 1, 8, 16, 32, and 64 bits,
addresses of 16 or 32 bits, or bit fields of 1 to 32 bits. The seven address
or 32 bits. The control registers (SR, VBR, SFC, DFC, CACR, CAAR, CRP, SRP,
TC, TT0, TT1, and MMUSR) vary in size according to function. Coprocessors
accordingly.
Each data register is 32 bits wide. Byte operands occupy the low-order 8 bits,
bits. When a data register is used as either a source or destination operand,
only the appropriate low-order byte or word (in byte or word operations,
used nor changed. The least significant bit of a long-word integer is addressed
is addressed as the width of the field minus one. If the width of the field plus
Quad-word data consists of two long words: for example, the product of 32-
bit multiply or the quotient of 32-bit divide operations (signed and unsigned).
Quad words may be organized in any two data registers without restrictions
of this data type, although the MOVEM instruction can be used to move a
quad word into or out of the registers.
defined by the instruction operation. Coprocessors are designed to support
special computation models that require very specific but widely varying
data operand types and sizes. Hence, coprocessor instructions can specify
operands of any size.
registers and the three stack pointers are used for address operands of 16
may define unique operand sizes and support them with on-chip registers
respectively) is used or changed; the remaining high-order portion is neither
MC68030 USER'S MANUAL
management
MOTOROLA