MC68030RC50C Freescale Semiconductor, MC68030RC50C Datasheet - Page 551

• Manufacturer Part Number: MC68030RC50C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC50C

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

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12-26
the memory is already enabled with its E input grounded). The last signal
the address corresponds to the encoded memory-mapped bank of SRAM.
Write operations use the DAS signal to qualify the address decode, which
The second section is the burst address generator which contains the four
select signals are only asserted during write operations when the processor
when the appropriate byte or bytes is being written to as indicated by the
AS is used to qualify the byte select signals to avoid spurious writes to
select (RDCS) signal, qualified with AS, controls the data latches only (since
generated by the PAL is the TERM signal. As the equation shows, TERM
consists of two events: one for read cycles and the other for write cycles.
lengthens write cycles to three clock periods. If a two-clock write cycle is
CBACK consolidation circuitry such that both are asserted when TERM is
asserted. The consolidation circuitry should have a maximum propagation
delay of 15 ns or less. If the system has no other synchronous memory or
grounded.
counters and the inverter. The counters serve to both buffer the MC68030's
address lines (A2 and A3) and to provide the next long-word address during
a burst operation. The 74F191s are asynchronously preset at the beginning
of every bus cycle when AS is negated. When AS asserts, the counting is
dependent on the CBREQ signal and the CLK signal. During writes, CBREQ
The third section contains the memory devices. The most important feature
of the memory devices used in this design is the separate data-in and data-
out pins, which allow the SRAMs to be constantly enabled before address
erates six memory-mapped signals: four byte select signals for write oper-
ations, a buffer control signal, and the cycle termination signal. The byte
SIZ0, SIZ1, A0, and A1 signals. The four signals, UUCS, UMCS, LMCS, and
LLCS, control data bits D24-D31, D16-D23, D8-15, and D0-D7 respectively.
memory before the address is valid. During read operations, the read chip
For read cycles, TERM is an address decode signal that is asserted whenever
required, this design can be modified to incorporate the address and data
latches used in Figure 12-12. TERM is connected to the system's STERM and
ports, TERM can be connected directly to STERM, and CBACI( may be
is always negated, and the counters serve only as address buffers. During
reads, if CBREQ asserts, the current value of counter bits QI:Q0 are incre-
mented on every falling clock edge of the MC68030's clock after AS asserts.
Four counters are used to provide enough drive capability to avoid an ad-
ditional buffer propagation delay. Each counter drives eight memory devices.
decode is complete without causing data bus contention. If the designer
larger block of memory (use A18-A20 instead of A16-A18). The PAL gen-
is addressing the 256K bytes contained in the memory bank, and then only
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