MC68030RC50C Freescale Semiconductor, MC68030RC50C Datasheet - Page 90

• Manufacturer Part Number: MC68030RC50C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC50C

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

3.2.2 Integer Arithmetic Instructions
M O T O R O L A
The integer arithmetic operations include the four basic operations of add
set includes ADD, CMP, and SUB instructions for both address and data
consist of 16 or 32 bits. The clear and negate instructions apply to all sizes
A set of extended instructions provides multiprecision and mixed-size arith-
Table 3-1 is a summary of the integer and floating-point data movement
(ADD), subtract (SUB), multiply (MUL), and divide (DIV) as well as arithmetic
compare (CMP, CMPM, CMP2), clear (CLR), and negate (NEG). The instruction
operations with all operand sizes valid for data operations. Address operands
of data operands.
Signed and unsigned MUL and DIV instructions include:
sign extended (EXT), and negate binary with extend (NEGX). Refer to Table
3-2 for a summary of the integer arithmetic operations.
operations.
metic. These instructions are add extended (ADDX), subtract extended (SUBX),
EXG
LEA
MOVE
MOVEA
MOVEM
MOVEP
MOVEQ
PEA
UNLK
LINK
• Word multiply to produce a long-word product
• Long-word multiply to produce and long-word or quad-word product
• Division of a long word divided by a word divisor (word quotient and
• Division of a long word or quad word dividend by a long-word divisor
Instruction
word remainder)
(long-word quotient and long-word remainder)
: <ea>,An
'list,<ea>
Rn, Rn
A n , # < d >
<ea>,<ea>
Dn, (d16,An)
(d16,An),Dn
<ea>
An
<ea>,An
<ea>,iist
#<data>,Dn
Operand Syntax
Table 3-1. Data Movement Operations
M C 6 8 0 3 0
32
32
8,16,32
16,32 I~ ,32
8 I) 32
32
32
16,32
16,32 I~ 32
16,32
16,32
Operand Size
U S E R ' S M A N U A L
Rn el) Rn
<ea> l) An
Sp 4 0 S P ; A n J(SP); SPI) An, SP+DOSP
source 0 destination
source l) listed registers
An l) SP; (SP) l) An; SP+4 J SP
listed registers J destination
Dn[31:24] 0 (An+d); Dn[23:16] 0 An + d + 2 ) ;
( A n - d ) I Dn[31:24]; ( A n + d + 2 ) 0 Dn[23:16];
immediate data ~ destination
SP 4 l) SP; <ea> I~ (SP)
Dn115:8I l) (An+d +4); Dn[7:0} l) ( A n + d + 6)
( A n ÷ d - 4 ) IF Dn[16:8]; ( A n + d + 6 ) l) Dn[7:0]
Operation
3-5
3