MC68030RC50C Freescale Semiconductor, MC68030RC50C Datasheet - Page 594

• Manufacturer Part Number: MC68030RC50C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC50C

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Tables; Instruction Timing, 11-24
Subroutine Calls; Nested, 3-30
Summary,
Supervisor Check Primitive, 10-40
Supervisor Only Protection, 9-48
Supervisor
Synchronization,
Synchronous
System
Table
STERM Signal, 5-6, 6-14, 6-16, 7-3, 7-6, 7-26ff
Structure Addressing, 2-25
Table Search, 9-30, 9-31
MOTOROLA
Termination Signal, 5-6, 6-14, 6-16, 7-3, 7-6,
Write Cycle,
Addressing Mode, 2-31
Translation Tree, 9-48
Cycle Signal Assertion Results, 7-79
Bead Cycle, 7-48
CIIN Asserted, CBACK Negated, Timing, 7-50
Read-Modify-Write Cycle Flowchart, 7-55
Control Instructions, 3-12
Stack, 2-36
Timing, 11-52
Coprocessor Instruction, 10-73-10-75
Effective Address Encoding, 2-22
M68000 Family, A-l-A-3
Signal, 5-12
Privilege Level, 4-2
Root Pointer, 1-9, 2-5, 9-13, 9-52, 9-54, 9-65
Bus, 7-95
Pipeline, 3-32
Bus Operation, 7-28, 7-29
Long Word Read Cycle Flowchart, 7-49
Read-Modify-Write Cycle, 7-52
Read-Modify-Write Cycle, CIIN Asserted, Timing,
Dynamic Allocation, 9-40
Sharing, 9-36
Index
Levels, Number of, 9-68
Paging, 9-37
Flowchart,
Initialization Flowchart, 9-42
7-26ff,
Wait States, CLOUT Asserted, Timing, 7-53
Table, 11-57
7-56
Script, 11-52
Flowchart, 7-52
Derivation, 9-10
Size Restrictions, 9-10
Example, 9-38
Example, 9-38
Detailed, 9-41
Simplified, 9-29
MC68030 USER'S MANUAL
Test and Set Instruction, 7-43
Tests, Condition, 3-17
Timing,
Take Address and Transfer Data Primitive, 10-48
Take Mid-Instruction Exception Primitive, 10-58
Take Post-Instruction Exception Primitive, 10-60
Take Pre-lnstruction Exception Primitive, 10-56
TAS Instruction, 7-43
Task Memory Map Definition, 9-67
TC, 1-9, 2-5, 9-8, 9-54
Asynchronous
Autovector Interrupt Acknowledge Cycle, 7-71
Misaligned
Processor-Generated Reset, 7-106
Retry Operation, Late,
Synchronous
Breakpoint Acknowledge Cycle, 7-74
Bus Arbitration, 7-96
Bus Error,
Bus Synchronization, 7-95
Halt Operation, 7-91
Initial Reset, 7-105
Interrupt Acknowledge Cycle, 7-69
Long Word,
Word Read Cycle, 32-Bit Port, 7-33
Word Write Cycle, 32-Bit Port, 7-39
Write Cycle, 32-Bit Port, 7-38
Without DSACKx, 7-84
Write, 7-12
Write Cycle, 16-Bit Port, 7-41
Write Cycle, 8-Bit Port, 7-40
Word to Word Transfer, 7-20
Asynchronous, 7-90
Synchronous, 7-91
Read Cycie, CIIN Asserted, CBACK Negated,
Read-Mod!fy-Write Cycle, CINN Asserted, 7-56
Byte Read Cycle, 32-Bit Port, 7-33
Byte Read-Modify-Write Cycle, 32-Bit Port, 7-45
Read Cycle, 32-Bit Port, 7-33
Exception Signaled, 7-77
Bus InacSve, 7-104
Late, STERM, 7-86
Late, With DSACKx, 7-85
Second Access, 7-88
Operand Request, Burst, CBACK and CIIN
Operand Request, Burst Fill Deferred, 7-65
Operand Request, Burst Request, CBACK
Operand Request, Burst Request, Wait States,
Read Cycle, 16-Bit Port, 7-35
Read Cycle, 32-Bit Port, 7-35
Read Cycle, 8-Bit Port, CLOUT Asserted, 7-34
Long-Word to Word Transfer, 7-11
Burst, 7-92
Byte Write Cycle, 32-Bit Port, 7-38
Late, Third Access, 7-87
Asserted, 7-66
7-63
7-50
Negated, 7-64
INDEX-11
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