MC68030RC50C Freescale Semiconductor, MC68030RC50C Datasheet - Page 590

• Manufacturer Part Number: MC68030RC50C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC50C

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Linked List
Logic, Byte Select, 12-9
Logical Address Map,
Logical Instructions, 3-6
Machine, Virtual, 1-14
MC68020
MC68851 Signals, 12-4
MC68881 Coprocessor, 12-6
MC68882 Coprocessor, 12-6
Mechanism, Data Transfer, 7-6
Memory,
Memory Access Time Calculations, 12-14-12-17
Memory Data Organization, 2-5
Memory Indirect Postindexed Mode, 2-14
Long Format
Long-Word Operand ~ u e s t ,
Long-Word Read Cycle,
Long-Word to Long-Word Transfer,
Long-Word to Word Transfer, 7-11
Long-Word Write Cycle,
Lookup, Function Code, 9-45, 9-46
Main Processor Detected
MOTOROLA
Table Descriptor, 9-24
Adapter Board, 12-1
Virtual, 1-12, 9-76
Deletion Example, 3-27
Insertion Example, 3-26
Function Code Lookup, 9-45
Shared Supervisor/User Address Space,
9-46
Early Termination Page Descriptor, 9-23
Indirect Descriptor, 9-28
Invalid Descriptor, 9-28
Page Descriptor, 9-26
Asynchronous, Flowchart, 7-32
Synchronous, Flowchart, 7-49
32-Bit Port, Timing, 7-35
8-Bit Port, ClOUTAsserted, Timing, 7-34
8-Bit Port, Timing, 7-40
Format Errors, 10-65
ProtOcol Violations, 10-61
Hardware Differences, 12-3
Software Differences, 12-4
Contiguous, 9-33, 9-35
Interface, 12-11
Burst, CBACK and CIIN Asserted, Timing, 7-66
Burst Fill Deferred, Timing, 7-65
Burst Reguest
16-Bit Port, Timing, 7-35
Misaligned, 7-20
Misaligne d, 7-17
16:Bit Port, Timing, 7-41
CBACK Negated, Timing, 7-64
Wait States, Timing, 7-63
Cachable, 7-20
M
MC68030 USER'S MANUAL
Memory Indirect Preindexed Mode, 2-15
Memory Management Unit, 1-15, 7-3, 7-36, 7-43ff,
Micro Bus Controller, 11-5
Microsequencer, 11-2
Mid-Instruction Stack Frame, 10-59
Misaligned
MMU, 1-15, 7-3, 7-36, 7-43ff, 9-1, 11-6
MMUDIS Signal, 5-10, 9-1, 9-2, 9-11, 12-1
MMUSR, 1-9, 2-5, 9-60-9-63
Mode,
Model, Programming, 1-6, 9-4
Modes, Addressing, 1-10, 2-8
Move Address Space Instruction, 7-74
MOVE Instruction,
9-1, 11-6
Cachable
Word to Word Transfer, 7-17
Word to Word Transfer Timing, 7-18
Long-Word to Long-Word Transfer, 7-20
Long-Word to Word Transfer, 7-15
Operand, 7-13, 7-19
Configuration Exception, 8-21, 9-62
Effective Address Timing Table, 11-58
Status Register, 1-9, 2-5, 9-60, 9-61, 9-62, 9-63
Absolute
Address Registers
Block Diagram, 9-2
Differences, 9-51
Disable Signal, 5-10, 9-1, 9-3, 9-11
Instruction Timing Table, 11-60
Instructions, 3-1, 9-62
Programming Model, 9-4
Register Side Effects, 9-61
Data Register Direct, 2-9
Memory Indirect
Program Counter
Special-Purpose, Timing Table, 11-37
Timing Table, 11-37
Word to Long-Word Transfer, 7-17
Word to Word Transfer, 7-20
Long-Word to Long-Word Transfer, 7-20
Timing, 7-16
Decoding, 9-61-9-63
Long Address, 2-20
Short Address, 2-20
Direct, 2-10
Indirect, 2-10
Indirect Displacement, 2-12
Indirect Index (Base Displacement), 2-13
Indirect Index (8-Bit Displacement), 2-12
Indirect Postincrement, 2-10
Indirect Predecrement, 2-11
Postindexed, 2-14
Preindexed, 2-15
Indirect Displacement, 2-16
Indirect Index (Base Displacement), 2-17
Indirect Index (8-Bit Displacement), 2-16
Memory Indirect Postindexed, 2:14
Memory Indirect Preindexed, 2-15
INDEX-7
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