MPC8321CVRAFDC Freescale Semiconductor, MPC8321CVRAFDC Datasheet - Page 2

• Manufacturer Part Number: MPC8321CVRAFDC
• Description: IC MPU PWRQUICC II 516-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8321CVRAFDC

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 333MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8323E-MDS-PB
• Maximum Clock Frequency: 333 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 16 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Overview
1
The MPC8323E incorporates the e300c2 (MPC603e-based) core built on Power Architecture®
technology, which includes 16 Kbytes of L1 instruction and data caches, dual integer units, and on-chip
memory management units (MMUs). The e300c2 core does not contain a floating point unit (FPU). The
MPC8323E also includes a 32-bit PCI controller, four DMA channels, a security engine, and a 32-bit
DDR1/DDR2 memory controller.
A new communications complex based on QUICC Engine technology forms the heart of the networking
capability of the MPC8323E. The QUICC Engine block contains several peripheral controllers and a
32-bit RISC controller. Protocol support is provided by the main workhorses of the device—the unified
communication controllers (UCCs). Note that the MPC8321 and MPC8321E do not support UTOPIA. A
block diagram of the MPC8323E is shown in
Each of the five UCCs can support a variety of communication protocols: 10/100 Mbps Ethernet, serial
ATM, HDLC, UART, and BISYNC—and, in the MPC8323E and MPC8323, multi-PHY ATM and ATM
support for up to OC-3 speeds.
2
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
4 TDM Ports
Integer Unit
Timers, Power Management,
Overview
I-Cache
Generators
16 KB
Parallel I/O
Baud Rate
(IU1)
Classic G2 MMUs
and JTAG/COP
e300c2 Core
QUICC Engine Block
Time Slot Assigner
Integer Unit
D-Cache
3 MII/RMII
Accelerators
16 KB
(IU2)
Single 32-Bit RISC CP
Serial Interface
Figure 1. MPC8323E Block Diagram
Multi-User
Security Engine (SEC 2.2)
RAM
Figure
MPC8323E
1 UL2/8-Bit
Serial DMA
2 Virtual
1.
DMAs
and
Protection and Configuration
System Interface Unit
Memory Controllers
32-Bit DDR1/DDR2
Interrupt Controller
Clock Synthesizer
4 Channel DMA
Bus Arbitration
PCI Controller
System Reset
Interface Unit
GPCM/UPM
Local Bus
DUART
(SIU)
I
2
C
Freescale Semiconductor
Local
DDR
PCI