MPC8321CVRAFDC Freescale Semiconductor, MPC8321CVRAFDC Datasheet - Page 67

• Manufacturer Part Number: MPC8321CVRAFDC
• Description: IC MPU PWRQUICC II 516-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8321CVRAFDC

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 333MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8323E-MDS-PB
• Maximum Clock Frequency: 333 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 16 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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2
3
22.4
The system PLL is controlled by the RCWL[SPMF] parameter.
encodings for the system PLL.
As described in
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk).
Freescale Semiconductor
DDR1/DDR2 memory bus frequency (MCLK)
Local bus frequency (LCLK n )
PCI input frequency (CLKIN or PCI_CLK)
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk , MCLK,
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
The DDR1/DDR2 data rate is 2× the DDR1/DDR2 memory bus frequency.
The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2× the
csb_clk frequency (depending on RCWL[LBCM]).
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
System PLL Configuration
System PLL VCO frequency = 2 × (CSB frequency) × (System PLL VCO
divider).
The VCO divider needs to be set properly so that the System PLL VCO
frequency is in the range of 300–600 MHz.
Section 22, “Clocking,”
3
Table 57. Operating Frequencies for PBGA (continued)
Characteristic
Table 58. System PLL Multiplication Factors
RCWL[SPMF]
0111–1111
2
0000
0001
0010
0011
0100
0101
0110
1
the LBCM, DDRCM, and SPMF parameters in the reset
NOTE
Multiplication Factor
System PLL
Reserved
Reserved
Reserved
× 2
× 3
× 4
× 5
× 6
Table 58
Max Operating Frequency
shows the multiplication factor
133
66
66
Table 59
Clocking
MHz
MHz
MHz
Unit
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