MPC8321CVRAFDC Freescale Semiconductor, MPC8321CVRAFDC Datasheet - Page 24

• Manufacturer Part Number: MPC8321CVRAFDC
• Description: IC MPU PWRQUICC II 516-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8321CVRAFDC

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 333MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8323E-MDS-PB
• Maximum Clock Frequency: 333 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 16 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Ethernet and MII Management
Figure 11
Figure 12
8.3
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock). The electrical characteristics for
MII, and RMII are specified in
Characteristics.”
24
At recommended operating conditions with OV
REF_CLK clock fall time V
Note:
1. The symbols used for timing specifications follow the pattern of t
inputs and t
receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. Also, t
the time data input signals (D) went invalid (X) relative to the t
Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For example, the subscript of t
convention is used with the appropriate letter: R (rise) or F (fall).
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
Ethernet Management Interface Electrical Characteristics
provides the AC test load.
shows the RMII receive AC timing diagram.
(first two letters of functional block)(reference)(state)(signal)(state)
REF_CLK
Parameter/Condition
RXD[1:0]
CRS_DV
RX_ER
IH
Table 26. RMII Receive AC Timing Specifications (continued)
Output
(max) to V
Figure 12. RMII Receive AC Timing Diagram
Section 8.1, “Ethernet Controller (10/100 Mbps)—MII/RMII Electrical
t
RMRDVKH
t
IL
RMXH
(min)
DD
RMX
of 3.3 V ± 10%.
t
RMX
represents the RMII (RM) reference (X) clock. For rise and fall times, the latter
Figure 11. AC Test Load
Z
0
= 50 Ω
Valid Data
RMRDXKL
Symbol
RMX
t
RMXF
t
RMXF
(first three letters of functional block)(signal)(state)(reference)(state)
for outputs. For example, t
clock reference (K) going to the low (L) state or hold time.
1
symbolizes RMII receive timing (RMR) with respect to
R
t
L
RMRDXKH
t
RMXR
= 50 Ω
Min
1.0
OV
Typical
DD
RMRDVKH
—
/2
Freescale Semiconductor
symbolizes RMII
Max
4.0
RMX
clock
Unit
ns
for