MPC8321CVRAFDC Freescale Semiconductor, MPC8321CVRAFDC Datasheet - Page 5

• Manufacturer Part Number: MPC8321CVRAFDC
• Description: IC MPU PWRQUICC II 516-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8321CVRAFDC

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 333MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8323E-MDS-PB
• Maximum Clock Frequency: 333 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 16 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1.3
The security engine is optimized to handle all the algorithms associated with IPSec, IEEE 802.11i™
standard, and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto
execution units (EUs). The execution units are:
1.4
The MPC8323E DDR1/DDR2 memory controller includes the following features:
1.5
The MPC8323E PCI controller includes the following features:
1.6
The programmable interrupt controller (PIC) implements the necessary functions to provide a flexible
solution for general-purpose interrupt control. The PIC programming model is compatible with the
MPC8260 interrupt controller, and it supports 8 external and 35 internal discrete interrupt sources.
Interrupts can also be redirected to an external interrupt controller.
Freescale Semiconductor
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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
Data encryption standard execution unit (DEU), supporting DES and 3DES
Advanced encryption standard unit (AESU), supporting AES
Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-256, and HMAC with any
algorithm
One crypto-channel supporting multi-command descriptor chains
Single 32-bit interface supporting both DDR1 and DDR2 SDRAM
Support for up to 266-MHz data rate
Support for two ×16 devices
Support for up to 16 simultaneous open pages
Supports auto refresh
On-the-fly power management using CKE
1.8-/2.5-V SSTL2 compatible I/O
Support for 1 chip select only
FCRAM, ECC, hardware/software calibration, bit deskew, QIN stage, or atomic logic are not
supported.
PCI Specification Revision 2.3 compatible
Single 32-bit data PCI interface operates up to 66 MHz
PCI 3.3-V compatible (not 5-V compatible)
Support for host and agent modes
On-chip arbitration, supporting three external masters on PCI
Selectable hardware-enforced coherency
DDR Memory Controller
Security Engine
PCI Controller
Programmable Interrupt Controller (PIC)
Overview
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