MPC8321CVRAFDC Freescale Semiconductor, MPC8321CVRAFDC Datasheet - Page 27

• Manufacturer Part Number: MPC8321CVRAFDC
• Description: IC MPU PWRQUICC II 516-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8321CVRAFDC

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 333MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8323E-MDS-PB
• Maximum Clock Frequency: 333 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 16 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 14
Freescale Semiconductor
LALE output fall to LAD output transition (LATCH hold time)
LALE output fall to LAD output transition (LATCH hold time)
Local bus clock (LCLK n ) to output valid
Local bus clock (LCLK n ) to output high impedance for LAD/LDP
Local bus clock (LCLK n ) duty cycle
Local bus clock (LCLK n ) jitter specification
Delay between the input clock (PCI_SYNC_IN) of local bus
output clock (LCLK n )
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
3. All signals are measured from OV
4. Input timings are measured at the pin.
5. t
6. t
7. t
8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
inputs and t
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock one(1).
LCLK0 (for all other inputs).
signaling levels.
on LAD output pins.
LAD output pins.
through the component pin is less than or equal to the leakage current specification.
LBOTOT1
LBOTOT2
LBOTOT3
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
provides the AC test load for the local bus.
should be used when RCWH[LALE] is set and the load on LALE output pin equals to the load on LAD output pins.
should be used when RCWH[LALE] is not set and the load on LALE output pin is at least 10 pF less than the load
should be used when RCWH[LALE] is set and the load on LALE output pin is at least 10 pF less than the load on
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter
Table 30. Local Bus General Timing Parameters (continued)
Output
DD
/2 of the rising/falling edge of LCLK0 to 0.4 × OV
Figure 14. Local Bus C Test Load
Z
0
= 50 Ω
(first two letters of functional block)(signal)(state)(reference)(state)
Symbol
t
t
for outputs. For example, t
t
t
LBOTOT2
LBOTOT3
LBKHOV
LBKHOZ
t
t
LBCDL
t
LBDC
LBRJ
LBK
1
R
clock reference (K) goes high (H), in this case for
L
= 50 Ω
Min
2.5
47
—
—
—
—
3
DD
OV
of the signal in question for 3.3-V
DD
LBIXKH1
/2
Max
400
1.7
53
—
—
3
4
symbolizes local bus
Unit
ns
ns
ns
ns
ps
ns
%
Local Bus
Notes
—
—
—
for
6
7
3
8
27