IC CODEC STEREO 5V 16BIT 68PLCC

AD1845JPZ

Manufacturer Part NumberAD1845JPZ
DescriptionIC CODEC STEREO 5V 16BIT 68PLCC
ManufacturerAnalog Devices Inc
TypeStereo Audio
AD1845JPZ datasheet
 


Specifications of AD1845JPZ

Resolution (bits)16 bNumber Of Adcs / Dacs2 / 2
Sigma DeltaYesDynamic Range, Adcs / Dacs (db) Typ81 / 82
Voltage - Supply, Analog4.75 V ~ 5.25 VVoltage - Supply, Digital4.75 V ~ 5.25 V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case68-PLCCSingle Supply Voltage (typ)5V
Single Supply Voltage (min)4.75VSingle Supply Voltage (max)5.25V
Package TypePLCCLead Free Status / RoHS StatusLead free / RoHS Compliant
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DATA AND CONTROL TRANSFERS
The AD1845 SoundPort Stereo Codec supports a DMA re-
quest/grant architecture for transferring data with the host com-
puter bus. One or two DMA channels can be supported.
Programmed I/O (PIO) mode is also supported for control
register accesses and for applications lacking DMA control.
PIO transfers can be made on one channel while the other is
performing DMA. Transfers to and from the AD1845
SoundPort Codec are asynchronous relative to the internal data
conversion clock. Transfers are buffered by FIFOs located in
the capture and playback paths.
Data Ordering
The number of byte-wide transfers required depends on the
data format selected. The AD1845 is designed for “little and
big endian” formats. In little endian format, the least significant
byte (i.e., occupying the lowest memory address) gets trans-
ferred first. Therefore, 16-bit data transfers require first trans-
ferring the least significant bits [7:0] and then transferring the
most significant bits [15:8], where Bit 15 is the most significant
bit in the word. In big endian format, byte ordering for the most
significant (MS) byte and least significant (LS) byte are swapped.
In addition, left channel data is always transferred before right
channel data with the AD1845. The following figures should
make these requirements clear.
SAMPLE 6
SAMPLE 5
SAMPLE 4
SAMPLE 3
MONO
MONO
MONO
BYTE 4
BYTE 3
BYTE 2
Figure 14. 8-Bit Mono Data Stream Sequencing
SAMPLE 3
SAMPLE 3
SAMPLE 2
SAMPLE 2
RIGHT
LEFT
BYTE 4
BYTE 3
BYTE 2
Figure 15. 8-Bit Stereo Data Stream Sequencing
SAMPLE 6
SAMPLE 5
SAMPLE 4
SAMPLE 3
LS
MS
LS
BYTES 3 AND 4
Figure 16. 16-Bit Mono Data Stream Sequencing, Little
Endian
REV. C
SAMPLE 3
RIGHT MS
Figure 17. 16-Bit Stereo Data Stream Sequencing, Little
Endian
SAMPLE 6 SAMPLE 5 SAMPLE 4 SAMPLE 4 SAMPLE 3 SAMPLE 2 SAMPLE 1
Figure 18. 16-Bit Mono Data Stream Sequencing, Big
Endian
SAMPLE 3
RIGHT LS
TIME
SAMPLE 2
SAMPLE 1
Figure 19. 16-Bit Stereo Data Stream Sequencing, Big
Endian
MONO
FIFO
BYTE 1
The AD1845 includes two 16-sample deep FIFOs. The FIFOs
are built into the capture and playback paths and are completely
transparent to the user and require no programming. The
FIFOs are active in MODE1 and MODE2.
TIME
The AD1845 maintains a continuous playback stream by re-
SAMPLE 1
SAMPLE 1
questing data from the host until the FIFO located in the play-
back path is full. As the FIFO empties, new samples are
requested to keep the playback FIFO full. In the event that the
RIGHT
LEFT
FIFO runs out of data and DACZ is reset to “0,” the last valid
BYTE 1
sample will be continuously played back. If DACZ is “1,” the
AD1845 will output a midscale value.
The FIFO located in the capture data path attempts to stay
TIME
empty by making requests of the host every sample period that it
contains valid data. When the host system cannot respond
SAMPLE 2
SAMPLE 1
during the same sample period, the capture FIFO starts filling,
and avoids a loss of data in the audio data stream.
Data Bus Drivers
MS
The AD1845 has built-in 8 or 16 mA bus drivers for interfacing
BYTES 1 AND 2
to the ISA bus. The drivers reduce the need for the off-chip
74_245 bus transceiver buffers in many applications. If higher
drive capability is required, 24 mA for example, the AD1845
generates the appropriate direction and enable signals. See
Figure 1 and refer to the Applications Circuits section of the
data sheet.
Control and Programmed I/O (PIO) Transfers
This simpler mode of transfers is used both for control register
accesses and programmed I/O. The 37 control and PIO data
registers cannot be accessed via DMA transfers. Playback PIO
–29–
AD1845
SAMPLE 3
SAMPLE 2
SAMPLE 2
SAMPLE 1
RIGHT LS
LEFT MS
BYTES 3 AND 4
BYTES 1 AND 2
LS
MS
LS
BYTES 3 AND 4
BYTES 1 AND 2
SAMPLE 3
SAMPLE 2
SAMPLE 2
SAMPLE 1
RIGHT MS
LEFT LS
BYTES 3 AND 4
BYTES 1 AND 2
TIME
SAMPLE 1
LEFT LS
TIME
MS
TIME
SAMPLE 1
LEFT MS