IC CODEC STEREO 5V 16BIT 68PLCC

AD1845JPZ

Manufacturer Part NumberAD1845JPZ
DescriptionIC CODEC STEREO 5V 16BIT 68PLCC
ManufacturerAnalog Devices Inc
TypeStereo Audio
AD1845JPZ datasheet
 


Specifications of AD1845JPZ

Resolution (bits)16 bNumber Of Adcs / Dacs2 / 2
Sigma DeltaYesDynamic Range, Adcs / Dacs (db) Typ81 / 82
Voltage - Supply, Analog4.75 V ~ 5.25 VVoltage - Supply, Digital4.75 V ~ 5.25 V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case68-PLCCSingle Supply Voltage (typ)5V
Single Supply Voltage (min)4.75VSingle Supply Voltage (max)5.25V
Package TypePLCCLead Free Status / RoHS StatusLead free / RoHS Compliant
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Switching between playback and capture in Single-Channel
DMA mode does not require changing the PPIO and CPIO bits
or passing through the Mode Change Enable state except for
initial setup. For setup, assign zeros to both PPIO and CPIO.
This configures both playback and capture for DMA. Following
setup, switching between playback and capture can be effected
entirely by setting and clearing the PEN and CEN control bits,
a technique which avoids having to enter Mode Change Enable.
Dual-Channel DMA
The AD1845 is designed to support full duplex DMA operation
by allowing simultaneous capture and playback. The Dual-
Channel DMA feature enables playback and capture DMA
requests and acknowledges to occur on separate DMA channels.
Capture and playback are enabled and set for DMA transfers.
In addition, Dual-Channel DMA must be set (SDC = 0). It is
not necessary to enter MCE (Mode Change Enable) to change
PEN and CEN (Playback and Capture Enable).
DMA Timing
Below, timing parameters are shown for 8-Bit Mono Sample
Read/Capture and Write/Playback DMA transfers in Figures 22
and 23. The same timing parameters apply to multi-byte trans-
fers. The relationship between timing signals is shown in Fig-
ures 24 and 25.
The Host Interrupt Pin (INT) will go HI after a sample transfer
in which the Current Count Register underflows.
ISA BUS BCLK
CDRQ OUTPUT
t
DRHD
t
DKSU
CDAK INPUT
t
DBDL
DBEN & DBDIR
OUTPUTS
t
STW
RD INPUT
t
RDDV
DATA7:0
OUTPUTS
Figure 22. 8-Bit Mono DMA Read/Capture Cycle
ISA BUS BCLK
PDRQ OUTPUT
t
DRHD
t
DKSU
PDAK INPUT
t
DSDL
DBEN OUTPUT
HI
DBDIR OUTPUT
t
STW
WR INPUT
t
WDSU
DATA7:0
OUTPUTS
Figure 23. 8-Bit Mono DMA Write/Playback Cycle
REV. C
ISA BUS BCLK
CDRQ /PDRQ
OUTPUTS
CDAK/PDAK
INPUTS
RD OR WR
INPUTS
DATA7:0
Figure 24. 8-Bit Stereo or 16-Bit Mono DMA Cycle
ISA BUS BCLK
CDRQ /PDRQ
OUTPUTS
CDAK/PDAK
INPUTS
RD OR WR
INPUTS
DATA7:0
Figure 25. 16-Bit Stereo DMA Interrupt
DMA Interrupt
Writing to the internal 16-bit Base Count Register sets up the
count value for the number of samples to be transferred. Note
that the number of bytes transferred for a given count will be a
function of the selected global data format. The internal Cur-
rent Count Register is updated with the current contents of the
Upper and Lower Base Count Registers when a write occurs to
t
DKHDb
the Upper Base Count Register.
The Current Count Register cannot be read by the host. Read-
ing the Base Count Registers will only read back the initializa-
t
tion values written to them.
DHD1
The Current Count Register decrements by one after every
sample transferred. An interrupt event is generated after the
Current Count Register is zero and an additional playback
sample is transferred. The INT bit in the Status Register always
reflects the current internal interrupt state defined above. The
external INT pin will only go active HI if the Interrupt Enable
(wIEN) bit in the Interface Configuration Register is set. If the
IEN bit is zero, the external INT pin will always stay LO, even
though the Status Register’s INT bit may be set.
t
DKHDa
t
DHD2
–31–
AD1845
t
BWDN
LEFT/
RIGHT/
LOW BYTE
HIGH BYTE
t
BWDN
LOW
HIGH
LOW
HIGH
BYTE
BYTE
BYTE
BYTE
LEFT
RIGHT
SAMPLE
SAMPLE