PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 135

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
5. After both monitor data bytes have been transferred to the IPAC, the controller
6. In the frame following the transition of the MX bit from active to inactive, the IPAC sets
7. If the IPAC is requested to return an answer it will commence with the response as
Error Treatment and Transmission Abort
In case the IPAC does not detect identical monitor messages in two successive frames,
transmission is not aborted. Instead the IPAC will wait until two identical bytes are
received in succession.
Transmission is aborted only if errors in the MR/MX handshake protocol occur. An abort
is indicated by setting the MR bit inactive for two or more IOM-2 frames. The controller
must react with EOM. This situation is illustrated in the following figure.
The response of the IPAC will always be sent immediately after the 2. byte has been
received and acknowledged.
transmits “End of Message” (EOM) by setting the MX bit inactive for two or more IOM
frames (frame No. 5-6).
the MR bit inactive (as was the case in step 4). As it detects EOM, it keeps the MR bit
inactive (frame No. 6). The transmission of the monitor command by the controller is
complete.
soon as the second controller byte was acknowledged (i.e. response starts in frame
5).
The procedure for the response is similar to that described in points 1-6 except for the
transmission direction. It is assumed that the controller does not latch monitor data.
For this reason one additional frame will be required for acknowledgment.
Transmission of the 2. monitor byte will be started by the IPAC in the frame
immediately following the acknowledgment of the first byte. The IPAC does not delay
the monitor transfer.
135
Functional Description
PSB 2115
PSF 2115
11.97