PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 39

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Data transmission is always performed out of the transmit FIFO by directly shifting the
contents of the XFIFOB via the serial transmit data pin (DU). Transmission is initiated by
setting CMDRB : XTF (08
In receive direction, the character currently assembled via the receive data line (DD) is
available in the RAL1 register. Additionally, in extended transparent mode 1 (MODEB:
MDS1, MDS0, ADM = 111), the received data is shifted into the RFIFOB.
This feature can be profitably used e.g. for:
• user specific protocol variations
• the application of character oriented protocols (e.g. BISYNC)
• test purposes, line intentionally violation of HDLC protocol rules (e.g. wrong CRC)
The valid timeslot for data access on IOM-2 can be selected by setting timeslot position
and timeslot length.
For a timeslot length greater than 8-bit (e.g. 16-bit) the access to the selected timeslots
on IOM-2 is not synchronized to the frame sync signal FSC. For example if the valid
16-bit timeslot is programmed to B1 and B2, the IPAC does not ensure that transmission
is started in B1 of the very first IOM-2 frame, it may also start with B2 and then continue
with B1 and B2 in the next frame.
It should be noted that in extended transparent mode 1 an invalid octett is output on
IOM-2 before the first valid octett from the XFIFOB is transmitted. In receive direction the
first 3 ocetetts of each 64-byte RFIFOB block are invalid and should be discarded.
2.1.9
If the extended transparent mode is selected, the IPAC supports the continuous
transmission of the transmit FIFO’s contents.
After having written 1 to 64 bytes to the XFIFOB, the command
XREP.XTF.XME
via the CMDR register (bit 7 … 0 = ‘00101010’ = 2AH) forces the IPAC to repeatedly
transmit the data stored in the XFIFOB via DU pin.
The cyclic transmission continues until a reset command (CMDRB : XRES) is issued,
after which continuous ‘1’-s are transmitted.
2.1.8
When programmed to the extended transparent mode via the MODEB register (MDS1,
MDS0 = 11), each channel of the IPAC supports fully transparent data transmission and
reception without HDLC framing overhead, i.e. without
• FLAG insertion and deletion
• CRC generation and checking
• Bit-stuffing mechanism.
In order to enable fully transparent data transfer, RAC bit in MODEB has to be reset and
FF
Semiconductor Group
H
has to be written to XAD1, XAD2 and RAH2.
Fully Transparent Transmission and Reception
Cyclic Transmission (Fully Transparent)
H
); end of transmission is indicated by EXIRB : EXE (40
39
Functional Description
PSB 2115
PSF 2115
H
11.97
).