PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 229

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
4.2.13
Value after reset: (not defined)
RAL1
The general function (READ/WRITE) and the meaning or contents of this register
depends on the selected operating mode:
– Non-auto mode (16-bit address) – WRITE only:
– Non-auto mode (8-bit address) – WRITE only:
– Transparent mode 1 (high byte address recognition) – READ only:
– Transparent mode 0 (no address recognition) – READ only:
– Extended transparent modes 0, 1 – READ only:
4.2.14
Value after reset: (not defined)
RAL2
Value of the second individual programmable low address byte. If a one byte address
field is selected, RAL2 is recognized as RESPONSE according to X.25 LAPB protocol.
RAL1 can be programmed with the value of the first individual low address byte.
According to X.25 LAPB protocol, the address in RAL1 is recognized as COMMAND
address.
RAL1 contains the byte following the high byte of the address in the receive frame
(i.e. the second byte after the opening flag).
RAL1 contains the first byte after the opening flag (first byte of received frame).
RAL1 contains the actual data byte currently assembled at the DD pin, bypassing the
HDLC receiver (fully transparent reception without HDLC framing).
RAL1 - Receive Address Byte Low Register 1 (READ/WRITE)
7
RAL2 - Receive Address Byte Low Register 2 (WRITE)
7
RAL1
RAL2
229
Detailed Register Description
0
0
PSB 2115
PSF 2115
(28/68)
(29/69)
11.97