PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 224

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

ADM … Address Mode
The meaning of this bit varies depending on the selected operating mode:
• Non-auto mode
In transparent modes, this bit differentiates between two sub-modes:
• Transparent mode
• Extended transparent mode; without HDLC framing.
Note: In extended transparent modes, the RAC bit must set to ‘0’ to enable fully
CFT … Continuous Frame Transmission
1… When CFT is set, the XPR interrupt is generated immediately after the CPU
accessible part of XFIFOB is copied into the transmitter section.
0… Otherwise the XPR interrupt is delayed until the transmission is completed (D-
Channel arbiter).
RAC … Receiver Active
Via RAC the HDLC receiver can be activated/deactivated.
0 … HDLC receiver inactive
1 … HDLC receiver active
In extended transparent modes this bit must be reset to enable fully transparent
reception!
TLP … Test Loop
When TLP is set, input and output of the HDLC controller are internally connected, i.e.
transmitter channel A to receiver channel A and
transmitter channel B to receiver channel B.
The receive B-channels on DD are disabled (data is ignored) and the transmit
B-channels on DU remain active (data is transmitted).
Semiconductor Group
Defines the length of the HDLC address field.
0 … 8-bit address field
1 … 16-bit address field
0 … transparent mode 0; no address recognition.
1 … transparent mode 1; high byte address recognition.
0 … extended transparent mode 0; received data in RAL1.
1 … extended transparent mode 1; received data in RFIFOB and RAL1.
transparent reception!
224
Detailed Register Description
PSB 2115
PSF 2115
11.97