PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 198

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

RSY
PU
AR
ARL
CVR
AIL
AI8
AI10
DC
C/I Indications
Abbreviation Indication
DR
RES
TM1
TM2
SLIP
Semiconductor Group
Deactivate Request
Reset
Test mode 1
Test mode 2
Slip detected
(LT-T only)
Resynchronization
during level detect
Power up
Activate request
Activate request loop
Far-end-code-violation After each multi-frame the receipt of at least one
Activate indication loop Loop A activated
Activate indication with
priority class 8
Activate indication with
priority class 10
Deactivate confirmation Clocks will be disabled, (in TE),
Remark
Reset acknowledge
TM1 acknowledge
TM2 acknowledge
Wander is larger than 50 s peak-to-peak (or 25
C/W/P-bit of the MON-8 Configuration Register)
Signal received, receiver not synchronous
IOM-2 interface clocking is provided
Info 2 received
illegal code violation is indicated six times. This
function must be enabled by setting the RCVE-
bit in the MON-8 Configuration Register.
Info 4 received,
D-channel priority is 8 or 9.
Info 4 received,
D-channel priority is 10 or 11.
quiescent state
Deactivation request via S/T-interface
Loop A closed
s peak-to-peak if programmed, refer to the
198
Operational Description
PSB 2115
PSF 2115
11.97