PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 19

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Pin No. Symbol Input (I)
27
28
3
2
Semiconductor Group
ALE
INT
DRQTB O
DRQRB O
Output (O)
I
OD
Function
Address Latch Enable
A HIGH on this line indicates an address on the
external address/data bus (multiplexed bus type only).
ALE also selects the microprocessor interface type
(multiplexed or non multiplexed).
Interrupt Request
This low active signal is activated when the IPAC
requests an interrupt. It is an open drain output.
DMA Request Transmitter (channel B)
The transmitter of the IPAC requests DMA data
transfer by activating this line.
The DRQTB remains HIGH as long as the transmit
FIFO requires data transfer.
The amount of data bytes to be transferred from
system memory to the IPAC (= byte count) must be
written first to the XBCH, XBCL register.
Always blocks of data (n x 64 bytes + REST, n=0, 1, ..)
are transferred till the byte count is reached.
DRQTB is deactivated immediately following the falling
edge of the last WR cycle.
Note: To support DMA for channel A, the DRQTA line
is available in TE mode only (see pin AUX0).
DMA Request Receiver (channel B)
The receiver of the IPAC requests DMA data transfer
by activating this line.
The DRQRB remains HIGH as long as the receive
FIFO requires data transfer, thus always blocks of data
(64, 32, 16, 8 or 4 bytes) are transferred.
DRQRB is deactivated immediately following the falling
edge of the last read cycle.
Note: To support DMA for channel A, the DRQRA line
is available in TE mode only (see pin AUX1).
19
PSB 2115
PSF 2115
Overview
11.97