PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 267

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
4.3.38
Value after reset: 00
MOCR
MRE1 ... MONITOR receive interrupt enable (IOM-channel 1)
MONITOR interrupt status MDR1 generation is enabled (1) or masked (0).
MRE0 ... MONITOR receive interrupt enable (IOM-channel 0)
MONITOR interrupt status MDR0, MER0 generation is enabled (1) or masked (0).
MRC1, 0 ... Determines the value of the MR-bit:
0: Determines the value of the MR-bit: MR always “1”. In addition, the MDR1/MDR0
interrupt is blocked, except for the first byte of a packet (if MRE 1/0=1).
1: MR internally controlled by the IPAC according to MONITOR channel protocol. In
addition, the MDR1/MDR0-interrupt is enabled for all received bytes according to the
MONITOR channel protocol (if MRE1,0=1).
MIE1 ... MONITOR interrupt enable (IOM-channel 1)
MONITOR interrupt status MER1, MDA1, MAB1 generation is enabled (1) or masked
(0).
MIE0 ... MONITOR interrupt enable (IOM-channel 0)
MONITOR interrupt status MDA0, MAB0 generation is enabled (1) or masked (0).
MXC1, 0 ... MX Bit Control (IOM-channel 1,0)
Determines the value of the MX-bit:
0.. MX always “1”.
1.. MX internally controlled by the IPAC according to MONITOR channel protocol.
MRE1 MRC1 MIE1 MXC1 MRE0 MRC0 MIE0 MXC0
MOCR - MONITOR Control Register (Write)
7
H
267
Detailed Register Description
0
PSB 2115
PSF 2115
11.97
(BA)