PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 241

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
XME ... Transmit Message End
By setting this bit to “1” the processor indicates that the data block written last in the
XFIFOD completes the corresponding frame. The IPAC terminates the transmission by
appending the CRC and the closing flag sequence to the data.
XRES ... Transmitter Reset
HDLC transmitter is reset and the XFIFOD is cleared of any data. This command can be
used by the processor to abort a frame currently in transmission.
Note: The maximum time between writing to the CMDRD register and the execution of
the command is 2.5 DCL clock cycles. During this time no further commands
should be written to the CMDRD register to avoid any loss of commands.
After an XPR interrupt further data has to be written to the XFIFOD and the
appropriate Transmit Command (XTF or XIF) has to be written to the CMDRD
register again to continue transmission, when the current frame is not yet
complete (see also XPR in ISTAD).
During frame transmission, the 0-bit insertion according to the HDLC bit-stuffing
mechanism is done automatically.
241
Detailed Register Description
PSB 2115
PSF 2115
11.97