PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 269

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PSB 2115
PSF 2115
Detailed Register Description
TEM ... Test Mode
In test mode (TEM=1) all layer-1 functions are disabled and the IPAC behaves like a D-
Channel HDLC controller (e.g. ICC PEB 2070) with a two channel HDLC
communications controller (e.g. HSCX-TE PSB 21525).
PDS ... Phase Deviation Select
Defines the phase deviation of the S-transceiver in TE or LT-T mode.
0: the phase deviation is two S-bits plus analog delay plus delay of the external circuitry.
1: the above phase deviation is reduced by 2 oscillator clocks (= 260 ns).
IDH ... IOM D-Channel Priority Handler
The state machine for D-channel priority handling on IOM-2 is
0: disabled
1: enabled
Note: This mode is used in intelligent NT applications.
The priority 8 or 10 is selected via bit SCFG:PRI.
SGO ... Stop/Go Bit Output (LT-T mode)
In LT-T mode the S/G bit can be output on pin AUX7. This may be used for test purposes
in order to observe the Stop/Go indications.
0: Pin AUX7 has default I/O functionality.
1: The S/G bit is output on pin AUX7.
ODS ... Output Driver Selection
Defines the output driver of the IOM-2 interface:
0: open drain
1: push pull
IOF ... IOM OFF
0: IOM interface is operational
1: IOM interface is switched off (DU, DD, FSC, DCL, BCL/SCLK, SDS high impedant).
IOF should be set to ’1’ if external devices connected to the IOM interface should be
“disconnected“ e.g. for power saving purposes or for not disturbing the internal IOM
connection between layer 1 and layer 2. However, the IPAC internal operation between
S-transceiver, B-channel and D-channel controller is independent of the IOF bit.
In Non-TE mode FSC and DCL (both input) are not switched off from the IOM-2 interface.
Semiconductor Group
269
11.97