PSB2115HV1.2 Lantiq, PSB2115HV1.2 Datasheet - Page 226

• Manufacturer Part Number: PSB2115HV1.2
• Manufacturer: Lantiq

Specifications of PSB2115HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.2.9
Value after reset: (not defined)
RBCLB
Together with RBCHB (bits RBC11 – RBC8), the length of the actual received frame
(1 … 4095 bytes) can be determined. These registers must be read by the CPU
following an RME interrupt.
4.2.10
Value after reset: (not defined)
RAH1
In operating modes that provide high byte address recognition, the high byte of the
received address is compared with the individual programmable values in RAH1, or
RAH2.
4.2.11
Value after reset: (not defined)
RAH2
RAH2 … Value of second individual programmable high address byte.
Note: RAH1, RAH2 registers are used in non-auto operating mode when a 2-byte
Semiconductor Group
address field has been selected (MODEB.ADM = 1) and in the transparent mode
1.
If a 1-byte address field is selected, RAH1 and RAH2 must be set to 00
RBCLB - Receive Byte Count Low for B-Channel (READ)
7
RBC7
RAH1 - Receive Address Byte High Register 1 (WRITE)
7
RAH2 - Receive Address Byte High Register 2 (WRITE)
7
RAH1
RAH2
226
Detailed Register Description
1
0
0
0
0
0
RBC0
0
0
PSB 2115
PSF 2115
H
.
(25/65)
(26/66)
(27/67)
11.97