AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 115

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

0
PCI Status Register
Offset 06h
The PCI Status register is a 16-bit register that contains
status information for the PCI bus related events. It is
located at offset 06h in the PCI Configuration Space.
Bit
15
IOEN
Name
PERR
host must program the PCI Mem-
ory Mapped I/O Base Address
register with a valid memory ad-
dress before setting MEMEN.
For accesses to the Expansion
ROM, the host must program the
PCI Expansion ROM Base Ad-
dress register at offset 30h with a
valid memory address before set-
ting MEMEN. The Am79C973/
Am79C975 controller will only re-
spond to accesses to the Expan-
sion ROM when both ROMEN
(PCI Expansion ROM Base Ad-
dress register, bit 0) and MEMEN
are set to 1. Since MEMEN also
enables the memory mapped ac-
cess
Am79C975 I/O resources, the
PCI Memory Mapped I/O Base
Address register must be pro-
grammed with an address so that
the device does not claim cycles
not intended for it.
MEMEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
Am79C973/Am79C975 controller
will ignore all I/O accesses when
IOEN is cleared. The host must
set IOEN before the first I/O ac-
cess to the device. The PCI I/O
Base Address register must be
programmed with a valid I/O ad-
dress before setting IOEN.
IOEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
the Am79C973/Am79C975 con-
troller detects a parity error.
The Am79C973/Am79C975 con-
troller samples the AD[31:0], C/
For memory mapped I/O, the
I/O Space Access Enable. The
Description
Parity Error. PERR is set when
to
the
Am79C973/
P R E L I M I N A R Y
Am79C973/Am79C975
14
13
SERR
RMABORT Received Master Abort. RM-
BE[3:0], and the PAR lines for a
parity error at the following times:
• In slave mode, during the ad-
dress phase of any PCI bus com-
mand.
• In slave mode, for all I/O, mem-
ory and configuration write com-
mands
Am79C973/Am79C975 controller
when data is transferred (TRDY
and IRDY are asserted).
• In master mode, during the data
phase of all memory read com-
mands.
In master mode, during the data
phase of the memory write com-
mand,
Am79C975 controller sets the
PERR bit if the target reports a
data parity error by asserting the
PERR signal.
PERR is not effected by the state
of the Parity Error Response en-
able bit (PCI Command register,
bit 6).
PERR is set by the Am79C973/
Am79C975
cleared by writing a 1. Writing a 0
has no effect. PERR is cleared by
H_RESET and is not affected by
S_RESET or by setting the STOP
bit.
SERR is set by the Am79C973/
Am79C975
cleared by writing a 1. Writing a 0
has no effect. SERR is cleared by
H_RESET and is not affected by
S_RESET or by setting the STOP
bit.
Signaled SERR. SERR is set
when the Am79C973/Am79C975
controller detects an address par-
ity error and both SERREN and
PERREN (PCI Command regis-
ter, bits 8 and 6) are set.
ABORT
Am79C973/Am79C975 controller
terminates a master cycle with a
master abort sequence.
is
that
the
set
controller
controller
select
Am79C973/
when
115
and
and
the
the