AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 93

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

Since setting MEMEN also enables memory mapped
access to the I/O resources, attention must be given to
the PCI Memory Mapped I/O Base Address register,
before enabling access to the Expansion ROM. The
host must set the PCI Memory Mapped I/O Base Ad-
dress register to a value that prevents the Am79C973/
Am79C975 controller from claiming any memory cy-
cles not intended for it.
During the boot procedure, the system will try to find an
Expansion ROM. A PCI system assumes that an Ex-
pansion ROM is present when it reads the ROM signa-
ture 55h (byte 0) and AAh (byte 1).
Direct Flash Access
Am79C973/Am79C975 controller supports Flash as an
Expansion ROM device, as well as providing a read/
wr ite data path to the Flash. The Am79C973/
Am79C975 controller will support up to 1 Mbyte of
Flash on the Expansion Bus. The Flash is accessed by
a read or write to the Expansion Bus Data por t
Figure 42. EPROM Only Configuration for the Expansion Bus (>64K EPROM)
Am79C973
EBUA_EBA[7:0]
EBDA[15:8]
AS_EBOE
EROMCS
EBD[7:0]
EBWE
P R E L I M I N A R Y
Am79C973/Am79C975
D-FF
'374
(BCR30). The user must load the upper address
EPADDRU (BCR 29, bits 3-0) and then set the FLASH
(BCR29, bit 15) bit to a 1. The Flash read/write utilizes
the PCI clock instead of the EBCLK during all ac-
cesses. EPADDRU is not needed if the Flash size is
64K or less, but still must be programmed. The user will
then load the lower 16 bits of address, EPADDRL (BCR
28, bits 15-0).
Flash/EPROM Read
A read to the Expansion Bus Data Port (BCR30) will
start a read cycle on the Expansion Bus Interface. The
A m 7 9 C 9 7 3 / A m 7 9 C 9 7 5 c o n t r o l l e r w i l l d r i v e
EBUA_EBA[7:0] with the most significant address byte
at the same time the Am79C973/Am79C975 controller
will drive AS_EBOE high to strobe the address in the
external ‘374 (D flip-flop). On the next clock, the
Am79C973/Am79C975 controller will drive EBDA[15:8]
and EBUA_EBA[7:0] with the middle and least signifi-
cant address bytes.
A[23:16]
A[15:8]
A[7:0]
DQ[7:0]
CS
OE
EPROM
21510D-47
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