AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 297

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

CSR32
CSR33
CSR34
CSR35
CSR36
CSR37
CSR38
CSR39
CSR4
CSR40
CSR41
CSR42
CSR43
CSR44
CSR45
CSR46
CSR47
CSR48
CSR49
CSR5
Next Transmit Descriptor Address
Next Transmit Descriptor Address
Current Transmit Descriptor Address
Current Transmit Descriptor Address
Next Next Receive Descriptor Address
Next Next Receive Descriptor Address
Next Next Transmit Descriptor Address
Next Next Transmit Descriptor Address
Test and Features Control . . . . . . . . . .129
Current Receive Byte Count . . . . . . . .143
Current Receive Status . . . . . . . . . . . . .143
Current Transmit Byte Count . . . . . . .143
Current Transmit Status . . . . . . . . . . . .143
Next Receive Byte Count . . . . . . . . . .143
Next Receive Status . . . . . . . . . . . . . . .144
Transmit Poll Time Counter . . . . . . . .144
Transmit Polling Interval . . . . . . . . . . .144
Receive Poll Time Counter . . . . . . . . .145
Receive Polling Interval . . . . . . . . . . . .145
Extended Control and Interrupt 1 . . . .130
Lower . . . . . . . . . . . . . . . . . . . . . . .142
Upper . . . . . . . . . . . . . . . . . . . . . . .142
Lower . . . . . . . . . . . . . . . . . . . . . . .142
Upper . . . . . . . . . . . . . . . . . . . . . . .142
Lower . . . . . . . . . . . . . . . . . . . . . . .142
Upper . . . . . . . . . . . . . . . . . . . . . . .142
Lower . . . . . . . . . . . . . . . . . . . . . . .143
Upper . . . . . . . . . . . . . . . . . . . . . . .143
P R E L I M I N A R Y
Am79C973/Am79C975
CSR58
CSR6
CSR60
CSR61
CSR62
CSR63
CSR64
CSR65
CSR66
CSR67 . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
CSR7
CSR72
CSR74
CSR76
CSR78
CSR8
CSR80
CSR82
CSR84
CSR85
CSR86
Software Style . . . . . . . . . . . . . . . . . . .145
RX/TX Descriptor Table Length . . . . .133
Previous Transmit Descriptor Address
Previous Transmit Descriptor Address
Previous Transmit Byte Count . . . . . . .148
Previous Transmit Status . . . . . . . . . . .148
Next Transmit Buffer Address
Next Transmit Buffer Address
Next Transmit Byte Count . . . . . .148, 149
Next Transmit Status . . . . . . . . . . . . . .149
Extended Control and Interrupt 2 . . . .133
Receive Ring Counter . . . . . . . . . . . . .149
Transmit Ring Counter . . . . . . . . . . . .149
Receive Ring Length . . . . . . . . . . . . . .149
Transmit Ring Length . . . . . . . . . . . . .149
Logical Address Filter 0 . . . . . . . . . . .136
DMA Transfer Counter and FIFO
Transmit Descriptor Address Pointer
DMA Address Register Lower . . . . . .152
DMA Address Register Upper . . . . . . .152
Buffer Byte Counter . . . . . . . . . . . . . .152
Lower . . . . . . . . . . . . . . . . . . . . . . .147
Upper . . . . . . . . . . . . . . . . . . .147, 148
Lower . . . . . . . . . . . . . . . . . . . . . . .148
Upper . . . . . . . . . . . . . . . . . . .148, 149
Threshold Control . . . . . . . . . . . . .150
Lower . . . . . . . . . . . . . . . . . . . . . . .152
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