AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 173

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

11
NOUFLO
No Underflow on Transmit. When
the NOUFLO bit is set to 1, the
Am79C973/Am79C975 controller
will not start transmitting the pre-
amble for a packet until the
Transmit Start Point (CSR80, bits
10-11) requirement (except when
XMTSP = 3h, Full Packet has no
meaning when NOUFLO is set to
1) has been met and the com-
plete packet has been DMA’d into
the Am79C973/Am79C975 con-
troller. The complete packet may
reside in any combination of the
Bus Transmit FIFO, the SRAM,
and the MAC Transmit FIFO, as
long as enough of the packet is in
the MAC Transmit FIFO to meet
the Transmit Start Point require-
ment. When the NOUFLO bit is
cleared to 0, the Transmit Start
Point is the only restriction on
when preamble transmission be-
gins for transmit packets.
The access time for the Expan-
sion ROM or for the EBDATA
(BCR30) device (t
write operations can be calculat-
ed by subtracting the clock to out-
put delay for the EBUA EBA[7:0]
outputs (t
the input to clock setup time for
Flash/EPRO inputs (t
the time defined by ROMTMG.
t
CLK_FAC - (t
For an adapter card application,
the value used for clock period
should be 30 ns to guarantee cor-
rect interface timing at the maxi-
mum clock frequency of 33 MHz.
Read accessible always; write
accessible only when the STOP
bit is set. ROMTMG is set to the
value of 1001b by H_RESET and
is not affected by S_RESET or
STOP. The default value allows
using an Expansion ROM with an
access time of 250 ns in a system
with a maximum clock frequency
of 33 MHz.
Setting the NOUFLO bit guaran-
tees
Am79C975 controller will never
ACC
= ROMTMG * CLK period *
that
v_A_D
v_A_D
the
) and by adding
) - (t
ACC)
Am79C973/
P R E L I M I N A R Y
s_D
s_D
Am79C973/Am79C975
) from
during
)
10
9
8
RES
MEMCMD
EXTREQ
Memory Command used for burst
suffer transmit underflows, be-
cause the arbiter that controls
transfers to and from the SRAM
guarantees a worst case latency
on transfers to and from the MAC
and Bus Transmit FIFOs such
that it will never underflow if the
complete
DMA’d
Am79C975
packet transmission begins.
The NOUFLO bit has no effect
when the Am79C973/Am79C975
controller is operating in the NO-
SRAM mode.
Read/Write accessible only when
either the STOP or the SPND bit
is set. NOUFLO is cleared to 0 af-
ter H_RESET or S_RESET and
is unaffected by STOP.
Reserved location. Written as ze-
ros and read as undefined.
read accesses to the transmit
buffer. When MEMCMD is set to
0, all burst read accesses to the
transmit buffer are of the PCI
command type Memory Read
Line (type 14). When MEMCMD
is set to 1, all burst read accesses
to the transmit buffer are of the
PCI command type Memory
Read Multiple (type 12).
Read accessible always; write
accessible only when either the
STOP or the SPND bit is set.
MEMCMD
H_RESET and is not affected by
S_RESET or STOP.
Extended Request. This bit con-
trols the deassertion of REQ for a
burst transaction. If EXTREQ is
set to 0, REQ is deasserted at the
beginning of a burst transaction.
(The
controller never performs more
than one burst transaction within
a single bus mastership period.)
In this mode, the Am79C973/
Am79C975 controller relies on
the PCI latency timer to get
enough bus bandwidth, in case
the system arbiter also removes
into
Am79C973/Am79C975
packet
is
controller
the
cleared
Am79C973/
has
before
been
173
by