AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 176

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

14
176
PREAD
EEPROM Read command bit.
When this bit is set to a 1 by the
host, the PVALID bit (BCR19, bit
15) will immediately be reset to a
0, and then the Am79C973/
Am79C975 controller will perform
a read operation of 82 bytes from
the EEPROM through the inter-
face. The EEPROM data that is
fetched during the read will be
stored in the appropriate internal
registers
Am79C973/Am79C975
ler. Upon completion of the EE-
PROM
Am79C973/Am79C975 controller
will assert the PVALID bit. EE-
PROM contents will be indirectly
accessible to the host through
read accesses to the Address
PROM (offsets 0h through Fh)
and through read accesses to
other EEPROM programmable
registers. Note that read access-
es from these locations will not
actually access the EEPROM it-
self, but instead will access the
Am79C973/Am79C975
lers internal copy of the EEPROM
contents. Write accesses to these
locations
Am79C973/Am79C975 controller
register contents, but the EE-
PROM locations will not be affect-
ed. EEPROM locations may be
accessed
BCR19.
EEPROM after H_RESET, as
well as to host-initiated PREAD
commands.
At the end of the read operation,
the PREAD bit will automatically
be reset to a 0 by the Am79C973/
Am79C975
PVALID will be set, provided that
an EEPROM existed on the inter-
face pins and that the checksum
for the entire 82 bytes of EE-
PROM was correct.
Note that when PREAD is set to a
1,
Am79C975 controller will no
longer respond to any accesses
directed toward it, until the
PREAD operation has completed
then
read
may
on
directly
the
controller
operation,
change
board
Am79C973/
P R E L I M I N A R Y
Am79C973/Am79C975
through
control-
control-
and
the
the
the
13
EEDET
successfully. The Am79C973/
Am79C975 controller will termi-
nate these accesses with the as-
sertion of DEVSEL and STOP
while TRDY is not asserted, sig-
naling to the initiator to discon-
nect and retry the access at a
later time.
If a PREAD command is given to
the Am79C973/Am79C975 con-
troller but no EEPROM is at-
tached to the interface pins, the
PREAD bit will be cleared to a 0,
and the PVALID bit will remain re-
set with a value of 0. This applies
to the automatic read of the EE-
PROM after H_RESET as well as
to host initiated PREAD com-
mands. EEPROM programmable
locations
Am79C973/Am79C975 controller
will be set to their default values
by such an aborted PREAD oper-
ation. For example, if the aborted
PREAD operation immediately
followed the H_RESET opera-
tion, then the final state of the EE-
PROM programmable locations
will be equal to the H_RESET
programming for those locations.
If a PREAD command is given to
the Am79C973/Am79C975 con-
troller and the auto-detection pin
(EESK/LED1/SFBD)
that no EEPROM is present, then
the EEPROM read operation will
still be attempted.
Note that at the end of the
H_RESET operation, a read of
the EEPROM will be performed
automatically. This H_RESET-
generated EEPROM read func-
tion will not proceed if the auto-
detection pin (EESK/LED1/SF-
BD) indicates that no EEPROM is
present.
Read accessible always; write
accessible only when either the
STOP or the SPND bit is set.
PREAD is set to 0 during
H_RESET and is unaffected by
S_RESET or the STOP bit.
EEPROM Detect. This bit indi-
cates the sampled value of the
on
board
indicates
the