AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 203

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

Initialization Block
Note: When SSIZE32 (BCR20, bit 8) is set to 0, the
software structures are defined to be 16 bits wide. The
base address of the initialization block must be aligned
to a DWord boundary, i.e., CSR1, bit 1 and 0 must be
cleared to 0. When SSIZE32 is set to 0, the initialization
block looks like Table 54.
Note: The Am79C973/Am79C975 controller performs
DWord accesses to read the initialization block. This
Bit(s)
15-4
3
2
1
0
IADR+0Ah
IADR+0Ch
IADR+0Eh
IADR+00h
IADR+02h
IADR+04h
IADR+06h
IADR+08h
IADR+10h
IADR+12h
IADR+14h
IADR+16h
Address
Full Duplex
Link Status
Reserved
AutoNEG
Speed
Name
Alert
Table 53. ANR24: Summary Status Register (Register 24)
Write as 0; Ignore on Read
1 = Link Status is up.
0 = Link Status is down.
1 = Operating in full duplex mode
0 = Operating in half duplex mode
1 = AutoNEG status has changed
0 = AutoNEG status unchanged
1 = Operating at 100 Mbps
0 = Operating at 10 Mbps
Bits 15-13
RLEN
TLEN
Table 54. Initialization Block (SSIZE32 = 0)
P R E L I M I N A R Y
Am79C973/Am79C975
Description
Bit 12
0
0
statement is always true, regardless of the setting of
the SSIZE32 bit.
When SSIZE32 (BCR20, bit 8) is set to 1, the software
structures are defined to be 32 bits wide. The base ad-
dress of the initialization block must be aligned to a
DWord boundary, i.e., CSR1, bits 1 and 0 must be
cleared to 0. When SSIZE32 is set to 1, the initialization
block looks like Table 55.
LADRF 15-00
LADRF 31-16
LADRF 47-32
LADRF 63-48
Bits 11-8
MODE 15-00
RDRA 15-00
PADR 15-00
PADR 31-16
PADR 47-32
TDRA 15-00
RES
RES
Bits 7-4
Read/
Write
R/O
R/O
R/O
R/O
0
TDRA 23-16
TDRA 23-16
H/W or Soft
Bits 3-0
Reset
0
0
0
0
1
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