AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 251

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

Notes:
1. Bit 15 and 13 are default 1.
2. M = bit (10, 9, 6, 5) and N = bit (4, 1, 0).
3. Similarly, other F
BCR2 Register Bits for setting SMIU Frequency
The frequency at which the SMIU will operate is calcu-
lated using the following expression: F
(M+1)*2
Where: F
Status
The SMIU of the Am79C975 controller provides two
registers to determine the status of the device.
The Am79C975 Status register indicates the status of
the current power state of the device (D0-D3). The
power state itself has no affect on the operation of the
SMIU. The management interface will operate in any
power state, as long as power is provided, i.e. opera-
tion in D
The Am79C975 Status register also indicates the sta-
tus of the normal operation of the device. The register
contains bits to indicated if the controller is stopped or
started and if the transceiver and receiver are enabled.
The Transceiver Status register provides the status of
the physical layer interface that is integrated into the
Am79C975 controller. The host can read this register to
determine if the controller is connected to an active net-
work (LINK set to 1), the speed of the connection (100
Mbps: SPEED=1, 10 Mbps: SPEED=0) and if the con-
nection is half duplex (DUPLEX=0) or full duplex (DU-
PLEX=1). In most cases, the transceiver will be
configured using the autonegotiation process.
AUTONEG_DONE will be set to ONE, when autonego-
tiation with the other end of the network cable has com-
pleted. LINK, SPEED and DUPLEX reflect the result of
the autonegotiation process. If AUTONEG_DONE is
ZERO, the LINK, SPEED and DULPEX bits reflect the
status of a manual transceiver configuration.
BCR2 (Bit No.)
combinations of M and N.
10
9
6
5
4
1
0
N+1
3cold
M is the value stored in bits D3-D6
N is the value stored in bits D0-D2.
I2C
kHz.
is not possible.
is the desired frequency (10-100 kHz)
I2C
can be programmed with proper
I2C_M3
I2C_M2
I2C_M1
I2C_M0
I2C_N2
I2C_N1
I2C_N0
Name
Position
I2C
P R E L I M I N A R Y
D6
D5
D4
D3
D2
D1
D0
Am79C973/Am79C975
= 2500/
Transmit Operation
The System Management Interface Unit (SMIU) of the
Am79C975 controller provides a separate 128-byte
Transmit Data memory to setup a management or alert
frame for transmission. The host must load the frame
byte by byte using one or multiple Block Write com-
mands to the Transmit Data port. The command code
of the Block Write command must be set to 36, the ad-
dress of the Transmit Data port. The byte count field
can have any value since it is ignored by the
Am79C975 controller. The device is capable of receiv-
ing any amount of transmit data even passed the limit
of 32 bytes as defined by the SMB specification. The lo-
cation within the Transmit Data memory where the next
byte is written to is controlled by the SMIU Transmit Ad-
dress register (MTX_ADR). This register will come up
cleared to 0 after H_RESET. With every byte write the
address register will auto-increment. This allows a
FIFO-type access to the Transmit Data memory and
the host does not need to keep track of the location he
is writing to. In addition, MTX_ADR can be set to any
address within the Transmit Data memory in order to
modify a specific location. The host must load all frame
information starting from the destination address and
ending with the last byte of data. The FCS is automati-
cally appended by the Am79C975 controller. The host
must load at least 60 bytes to the Transmit Data mem-
ory in order to create a legal length frame. Padding is
not suppor ted by the SMIU. The setting of the
APAD_XMT bit in CSR4 only effects the transmission
of normal frames and not of management frames.
The SMIU provides a set of registers that contain net-
work address information. The address information can
be used to setup the alert frame. The six Node IEEE
Address registers contain the unique 48-bit address of
the station, the Am79C975 controller is used in. The
four Node IP Address registers contain the 32-bit IP ad-
dress of that station. The six Management Station
IEEE Address registers contain the unique 48-bit ad-
dress of the station that is used as the management
console in the network. The four Management Station
IP Address registers contain the 32-bit IP address of
the management console. All 3 sets of registers are
loaded from the EEPROM. The Node IP Address, Man-
agement IEEE Address and Management IP Address
registers can also be used as general purpose regis-
ters to load information stored in the EEPROM and
make it accessible via the serial management interface
to the external host.
The host must setup the Transmit Message Length reg-
ister (MTX_LEN) with the number of bytes loaded to
the Transmit Data memory so that the MAC knows how
many bytes to transmit. The host is responsible to load
a valid value into the Transmit Message Length regis-
ter. Any value below 60 will create a runt frame on the
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