AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 53

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

When the preemption occurs after the counter has
counted down to 0, the Am79C973/Am79C975 control-
ler will finish the current data phase, deassert FRAME,
finish the last data phase, and release the bus. Note
that it is important for the host to program the PCI La-
tency Timer according to the bus bandwidth require-
ment of the Am79C973/Am79C975 controller. The host
can determine this bus bandwidth requirement by read-
ing the PCI MAX_LAT and MIN_GNT registers.
Figure 20 assumes that the PCI Latency Timer has
counted down to 0 on clock 7.
Master Abort
The Am79C973/Am79C975 controller will terminate its
cycle with a Master Abort sequence if DEVSEL is not
asserted within 4 clocks after FRAME is asserted.
Master Abor t is treated as a fatal error by the
Am79C973/Am79C975 controller. The Am79C973/
DEVSEL
FRAME
TRDY
STOP
IRDY
C/BE
REQ
GNT
CLK
PAR
AD
1
DEVSEL is sampled
Figure 18. Target Abort
2
ADDR
0111
3
PAR
4
DATA
0000
5
PAR
6
P R E L I M I N A R Y
21510D-23
Am79C973/Am79C975
7
Am79C975 controller will reset all CSR locations to
their STOP_RESET values. The BCR and PCI config-
uration registers will not be cleared. Any on-going net-
wor k transmission is ter minated in an order ly
sequence. If less than 512 bits have been transmitted
onto the network, the transmission will be terminated
immediately, generating a runt packet. If 512 bits or
more have been transmitted, the message will have the
current FCS inverted and appended at the next byte
boundary to guarantee an FCS error is detected at the
receiving station.
RMABORT (in the PCI Status register, bit 13) will be set
to indicate that the Am79C973/Am79C975 controller
has terminated its transaction with a master abort. In
addition, SINT (CSR5, bit 11) will be set to 1. When
SINT is set, INTA is asserted if the enable bit SINTE
(CSR5, bit 10) is set to 1. This mechanism can be used
to inform the driver of the system error. The host can
read the PCI Status register to determine the exact
cause of the interrupt. See Figure 21.
Parity Error Response
During every data phase of a DMA read operation,
when the target indicates that the data is valid by as-
serting TRDY, the Am79C973/Am79C975 controller
samples the AD[31:0], C/BE[3:0] and the PAR lines for
a data parity error. When it detects a data parity error,
the controller set PERR (PCI Status register, bit 15) to
1. When reporting of that error is enabled by setting
PERREN (PCI Command register, bit 6) to 1, the
Am79C973/Am79C975 controller also drives the
PERR signal low and sets DATAPERR (PCI Status reg-
ister, bit 8) to 1. The assertion of PERR follows the cor-
rupted data/byte enables by two clock cycles and PAR
by one clock cycle.
Figure 22 shows a transaction that has a parity error in
the data phase. The Am79C973/Am79C975 controller
asserts PERR on clock 8, two clock cycles after data is
valid. The data on clock 5 is not checked for parity,
since on a read access PAR is only required to be valid
one clock after the target has asserted TRDY. The
Am79C973/Am79C975 controller then drives PERR
high for one clock cycle, since PERR is a sustained tri-
state signal.
During every data phase of a DMA write operation, the
Am79C973/Am79C975 controller checks the PERR
input to see if the target reports a parity error. When it
sees the PERR input asserted, the controller sets
PERR (PCI Status register, bit 15) to 1. When PER-
REN (PCI Command register, bit 6) is set to 1, the
A m 7 9 C 9 7 3 / A m 7 9 C 9 7 5 c o n t r o l l e r a l s o s e t s
DATAPERR (PCI Status register, bit 8) to 1.
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