AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 154

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

CSR112: Missed Frame Count
Bit
31-16 RES
15-0
CSR114: Receive Collision Count
Bit
31-16 RES
15-0
154
MFC
RCC
Name
Name
setting of the MERRM bit (CSR3,
bit 11) and the IENA bit (CSR0,
bit 6).
Reserved locations. Written as
zeros and read as undefined.
Missed Frame Count. Indicates
the number of missed frames.
Reserved locations. Written as
zeros and read as undefined.
Receive Collision Count. Indi-
cates the total number of colli-
sions
receiver since the last reset of the
counter.
The value in this register is inter-
preted as the unsigned number of
bus clock periods divided by two,
(i.e., the value in this register is
given in 0.1 ms increments.) For
example, the value 0600h (1536
decimal) will cause a MERR to be
indicated after 153.6 ms of bus
latency. A value of 0 will allow an
infinitely long bus latency, i.e.,
bus timeout error will never oc-
cur.
Read/Write accessible only when
either the STOP or the SPND bit
is set. This register is set to
0600h
S_RESET and is unaffected by
STOP.
MFC will roll over to a count of 0
from the value 65535. The MFCO
bit of CSR4 (bit 8) will be set each
time that this occurs.
Read accessible always. MFC is
read only, write operations are ig-
nored.
H_RESET or S_RESET or by
setting the STOP bit.
RCC will roll over to a count of 0
from the value 65535. The
Description
Description
encountered
MFC
by
is
H_RESET
cleared
P R E L I M I N A R Y
Am79C973/Am79C975
by
the
by
or
CSR116: OnNow Power Mode Register
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-14 RES
13 LCMODE_D3C. This bit is a read/write from the
12 MPPEN_D3C
11 PMAT_MODE_D3C
Name
Description
RCVCCO bit of CSR4 (bit 5) will
be set each time that this occurs.
Read accessible always. RCC is
read only, write operations are ig-
nored.
H_RESET or S_RESET, or by
setting the STOP bit.
Reserved locations. Written as
zeros and read as undefined.
PCI bus and is reset only at
power-on. This bit is not written
from the EEPROM. Power man-
agement software can set this bit
before going to D3cold and even
if there is a reset and the EE-
PROM loads because of an incor-
rect PG signal, the control bit will
not be changed. This bit is OR’ed
with LCMODE (CSR116 bit 8) for
OnNow link chnage, but not for
hardware link change
This bit is read/write from the the
PCI bus and is reset only at
power-on. This bit is not written
from the EEPROM. Power man-
agement software can set this bit
before going to D3cold and even
if there is a reset and the EE-
PROM loads because of an incor-
rect PG signal, the control bit will
not be changed. This bit is OR’ed
with MPPEN (CSR116 bit 4) for
both hardware magic packet or
OnNow magic packet.
This bit is read/write from the the
PCI bus and is reset only at
power-on. This bit is not written
from the EEPROM. Power man-
agement software can set this bit
before going to D3cold and even
if there is a reset and the EE-
PROM loads because of an incor-
rect PG signal, the control bit will
not be changed. This bit is OR’ed
with PMAT_MODE (BCR45 bit 7)
for OnNow magic packet.
RCC
is
cleared
by