AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 211

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

22-16 RES
15-12 ONES
11-00 BCNT
TMD2
Bit
31
BUFF
Name
when a parity error occurred on
the bus interface during a data
transfers from the transmit buffer
associated with this descriptor.
The Am79C973/Am79C975 con-
troller will only set BPE when the
advanced parity error handling is
enabled by setting APERREN
(BCR20, bit 10) to 1. BPE is set
by the Am79C973/Am79C975
controller and cleared by the
host.
Reserved locations.
These four bits must be written as
ones. This field is written by the
host and unchanged by the
Am79C973/Am79C975
ler.
Buffer Byte Count is the usable
length of the buffer pointed to by
this descriptor, expressed as the
two’s complement of the length of
the buffer. This is the number of
bytes from this buffer that will be
transmitted by the Am79C973/
Am79C975 controller. This field is
written by the host and is not
changed by
Am79C975 controller. There are
no minimum buffer size restric-
tions.
Buffer
Am79C973/Am79C975 controller
during transmission when the
Am79C973/Am79C975 controller
does not find the ENP flag in the
current descriptor and does not
own the next descriptor. This can
occur in either of two ways:
This bit does not exist, when the
Am79C973/Am79C975 controller
is programmed to use 16-bit soft-
ware structures for the descriptor
ring entries (BCR20, bits 7-0,
SWSTYLE is cleared to 0).
1. The OWN bit of the next buffer
is 0.
Description
error
is
the Am79C973/
set
P R E L I M I N A R Y
Am79C973/Am79C975
by
control-
the
30
29
28
27
UFLO
EXDEF
LCOL
LCAR
Underflow error indicates that the
Late Collision indicates that a col-
2. FIFO underflow occurred be-
fore the Am79C973/Am79C975
controller obtained the STATUS
byte (TMD1[31:24]) of the next
descriptor. BUFF is set by the
Am79C973/Am79C975 controller
and cleared by the host.
If a Buffer Error occurs, an Un-
derflow Error will also occur.
BUFF is set by the Am79C973/
Am79C975
cleared by the host.
transmitter has truncated a mes-
sage because it could not read
data from memory fast enough.
UFLO indicates that the FIFO has
emptied before the end of the
frame was reached.
When DXSUFLO (CSR3, bit 6) is
cleared to 0, the transmitter is
turned off when an UFLO error
occurs (CSR0, TXON = 0).
When DXSUFLO is set to 1, the
Am79C973/Am79C975 controller
gracefully
UFLO error. It scans the transmit
descriptor ring until it finds the
start of a new frame and starts a
new transmission.
UFLO is set by the Am79C973/
Am79C975
cleared by the host.
Excessive Deferral. Indicates that
the transmitter has experienced
Excessive Deferral on this trans-
mit frame, where Excessive De-
ferral is defined in the ISO 8802-3
(IEEE/ANSI 802.3) standard. Ex-
cessive Deferral will also set the
interrupt bit EXDINT (CSR5, bit
7).
lision has occurred after the first
channel slot time has elapsed.
The Am79C973/Am79C975 con-
troller does not retry on late colli-
sions. LCOL is set by the
Am79C973/Am79C975 controller
and cleared by the host.
Loss of Carrier is set when the
carrier
Am79C973/Am79C975 controller
is
recovers
lost
controller
controller
during
from
211
and
and
an
an