AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 49

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

Basic Non-Burst Write Transfer
By default, the Am79C973/Am79C975 controller uses
non-burst cycles in all bus master write operations. All
Am79C973/Am79C975 controller non-burst write ac-
cesses are of the PCI command type Memory Write
(type 7). The byte enable signals indicate the byte
lanes that have valid data. The Am79C973/Am79C975
controller typically performs more than one non-burst
write transaction within a single bus mastership period.
FRAME is dropped between consecutive non-burst
write cycles. REQ, however, stays asserted until
FRAME is asser ted for the last transaction. The
Am79C973/Am79C975 supports zero wait state write
cycles except with descriptor write transfers. (See the
section Descriptor DMA Transfers for the only excep-
tion.) It asserts IRDY immediately after the address
phase.
Figure 14 shows two non-burst write transactions. The
first transaction has two wait states. The target inserts
one wait state by asserting DEVSEL one clock late and
another wait state by also asserting TRDY one clock
late. The second transaction shows a zero wait state
write cycle. The target asserts DEVSEL and TRDY in
the same cycle as the Am79C973/Am79C975 control-
ler asserts IRDY.
DEVSEL
FRAME
TRDY
IRDY
C/BE
REQ
GNT
CLK
PAR
AD
1
DEVSEL is sampled
2
Figure 14. Non-Burst Write Transfer
ADDR
0111
P R E L I M I N A R Y
3
Am79C973/Am79C975
PAR
4
DATA
BE
5
PAR
Basic Burst Write Transfer
The Am79C973/Am79C975 controller supports burst
mode for all bus master write operations. The burst
mode must be enabled by setting BWRITE (BCR18, bit
5). To allow burst transfers in descriptor write opera-
tions, the Am79C973/Am79C975 controller must also
be programmed to use SWSTYLE 3 (BCR20, bits 7-0).
All Am79C973/Am79C975 controller burst write trans-
fers are of the PCI command type Memory Write (type
7). AD[1:0] will both be 0 during the address phase in-
dicating a linear burst order. The byte enable signals in-
dicate the byte lanes that have valid data.
The Am79C973/Am79C975 controller will always per-
form a single burst write transaction per bus mastership
period, where transaction is defined as one address
ph as e an d o ne or mul ti pl e da ta p ha s es. Th e
Am79C973/Am79C975 controller supports zero wait
state write cycles except with the case of descriptor
write transfers. (See the section Descriptor DMA Trans-
fers for the only exception.) The device asserts IRDY
immediately after the address phase and at the same
time starts sampling DEVSEL. FRAME is deasserted
when the next to last data phase is completed.
6
7
ADDR
0111
8
DATA
PAR
BE
9
PAR
10
49