M29W320DT70N6 STMicroelectronics, M29W320DT70N6 Datasheet - Page 13

• Manufacturer Part Number: M29W320DT70N6
• Description: Flash 4Mx8 or 2Mx16 70ns
• Manufacturer: STMicroelectronics

Specifications of M29W320DT70N6

• Data Bus Width: 8 bit, 16 bit
• Memory Type: NOR Flash
• Memory Size: 32 Mbit
• Architecture: Sectored
• Interface Type: CFI
• Access Time: 70 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 10 mA
• Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSOP-1-48
• Organization: 4 MB x 8
• Lead Free Status / Rohs Status: Details

BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Figure 8. and Table 2., Bus Operations, for a sum-
mary. Typically glitches of less than 5ns on Chip
Enable or Write Enable are ignored by the memory
and do not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, V
and Output Enable and keeping Write Enable
High, V
value, see Figure 13., Read Mode AC Waveforms,
and Table 11., Read AC Characteristics, for de-
tails of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, V
Write operation. See Figure 14. and Figure 15.,
Write AC Waveforms, and Table 12. and Table
13., Write AC Characteristics, for details of the tim-
ing requirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V
Standby. When Chip Enable is High, V
memory enters Standby mode and the Data In-
Figure 8. Bus Operations, BYTE = V
Note: X = V
Bus Read
Bus Write
Output Disable
Standby
Read Manufacturer
Code
Read Device Code
Operation
IH
IH
IL
. The Data Inputs/Outputs will output the
.
or V
IH
.
V
V
V
V
V
E
X
IH
IL
IL
IL
IL
IH
, during the whole Bus
V
V
V
V
V
G
X
IH
IH
IL
IL
IL
IL
, to Chip Enable
V
V
V
V
V
W
X
IH
IH
IH
IH
IL
IL
Cell Address
Command Address
X
X
A0 = V
Others V
A0 = V
A9 = V
IH
, the
DQ15A–1, A0-A20
IL
IH
ID
Address Inputs
, A1 = V
, A1 = V
, Others V
IL
or V
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, I
be held within V
level see Table 10., DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
til the operation completes.
Automatic Standby. If CMOS levels (V
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require V
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Figure 8. and Table 2., Bus Operations.
Block Protect and Chip Unprotect. Each
can be separately protected against accidental
Program or Erase. The whole chip can be unpro-
tected to allow the data inside the blocks to be
changed.
Block Protect and Chip Unprotect operations are
described in APPENDIX C..
IH
IL
IL
, A9 = V
,
IL
or V
CC3
IH
ID
,
, for Program or Erase operations un-
ID
CC
to be applied to some pins.
M29W320DT, M29W320DB
± 0.2V. For the Standby current
DQ14-DQ8
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Data Inputs/Outputs
CC2
, Chip Enable should
CAh (M29W320DT)
CBh (M29W320DB)
Data Output
Data Input
DQ7-DQ0
Hi-Z
Hi-Z
20h
CC
CC2
± 0.2V)
. The
block
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