M29W320DT70N6 STMicroelectronics, M29W320DT70N6 Datasheet - Page 5

• Manufacturer Part Number: M29W320DT70N6
• Description: Flash 4Mx8 or 2Mx16 70ns
• Manufacturer: STMicroelectronics

Specifications of M29W320DT70N6

• Data Bus Width: 8 bit, 16 bit
• Memory Type: NOR Flash
• Memory Size: 32 Mbit
• Architecture: Sectored
• Interface Type: CFI
• Access Time: 70 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 10 mA
• Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSOP-1-48
• Organization: 4 MB x 8
• Lead Free Status / Rohs Status: Details

SUMMARY DESCRIPTION
The M29W320D is a 32 Mbit (4Mb x8 or 2Mb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be per-
formed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
The blocks in the memory are asymmetrically ar-
ranged, see Figure 6. and Figure 7., Table 19. and
Table 20.The first or last 64 Kbytes have been di-
vided into four additional blocks. The 16 Kbyte
Boot Block can be used for small initialization code
to start the microprocessor, the two 8 Kbyte Pa-
rameter Blocks can be used for parameter storage
and the remaining 32 Kbyte is a small Main Block
where the application may be stored.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP48 (12 x 20mm)
TFBGA63 (7x11mm, 0.8mm pitch) and TFBGA48
(6x8mm, 0.8mm pitch) packages. The memory is
supplied with all the bits erased (set to 1).
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A20
DQ0-DQ7
DQ8-DQ14
DQ15A–1
E
G
W
RP
RB
BYTE
V
V
V
NC
A0-A20
CC
SS
PP
BYTE
/WP
RP
W
G
E
21
Address Inputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Input/Output or Address Input
Chip Enable
Output Enable
Write Enable
Reset/Block Temporary Unprotect
Ready/Busy Output
Byte/Word Organization Select
Supply Voltage
V
Ground
Not Connected Internally
PP
M29W320DT
M29W320DB
V CC
M29W320DT, M29W320DB
V SS
/Write Protect
V PP /WP
15
DQ0-DQ14
DQ15A–1
RB
AI90189B
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