MCP3903-I/SS Microchip Technology, MCP3903-I/SS Datasheet - Page 25

• Manufacturer Part Number: MCP3903-I/SS
• Description: IC AFE 24BIT 64KSPS 28SSOP
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MCP3903-I/SS

• Featured Product: MCP3903 Six Channel ΔΣ A/D Converter
• Number Of Bits: 24
• Number Of Channels: 6
• Power (watts): -
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 3.6 V
• Package / Case: 28-SSOP (0.209", 5.30mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.4
All ADCs present in the MCP3903 include a decimation
filter that is a third-order sinc (or notch) filter. This filter
processes the multi-bit bitstream into 16 or 24 bits
words (depending on the WIDTH configuration bit). The
settling time of the filter is 3 DMCLK periods. It is
recommended to discard unsettled data to avoid data
corruption which can be done easily by setting the
DR_LTY bit high in the STATUS/COM register.
The resolution achievable at the output of the sinc filter
(the output of the ADC) is dependant on the OSR and
is summarized in the following table:
TABLE 5-2:
For 24 -bit output mode (WIDTH = 1), the output of the
sinc filter is padded with least significant zeros for any
resolution less than 24 bits.
For 16-bit output modes, the output of the sinc filter is
rounded to the closest 16-bit number in order to
conserve only 16-bit words and to minimize truncation
error.
The gain of the transfer function of this filter is 1 at each
multiple of DMCLK (typically 1 MHz) so a proper
anti-aliasing filter must be placed at the inputs to
attenuate the frequency content around DMCLK, and
keep the desired accuracy over the baseband of the
converter. This anti-aliasing filter can be a simple
first-order RC network, with a sufficiently low time
constant to generate high rejection at DMCLK
frequency.
EQUATION 5-1:
Where:
© 2011 Microchip Technology Inc.
0
0
1
1
OSR<1:0>
SINC
H z ( )
0
1
0
1
3
z
Filter
ADC RESOLUTION VS. OSR
=
=
exp
⎛
⎜
⎝
SINC FILTER TRANSFER
FUNCTION H(Z)
-------------------------------- -
OSR 1 z
⎛
⎝
1 z
--------------------- -
DMCLK
–
OSR
128
256
(
2πfj
32
64
–
OSR
–
1 –
⎞
⎠
)
⎞
⎟
⎠
3
No Missing
Resolution
Codes
(bits)
ADC
17
20
23
24
The Normal-Mode Rejection Ratio (NMRR), or gain of
the transfer function, is shown in the following equation:
EQUATION 5-2:
or:
where:
Figure 5-2
FIGURE 5-2:
MCLK = 4 MHz, OSR = 64, PRESCALE = 1.
-100
-120
-20
-40
-60
-80
20
0
1
NMRR f ( )
shows the sinc filter frequency response:
NMRR f ( )
10
sin
=
c x ( )
Input Frequency (Hz)
100
MAGNITUDE OF
FREQUENCY RESPONSE
H(f)
SINC Filter Response with
--------------------------------------------- -
=
sin
sin
=
c
---------------------------- -
c
sin
sin
⎛
⎝
⎛
⎝
1000
-------------- -
π
sin
π
c π
c π
⋅
MCP3903
⋅
⎛
⎝
⎛
⎝
x
--------------------- -
DMCLK
x ( )
--------------------
DRCLK
⋅
⋅
---- -
f
10000
--- -
f
f
f
f
D
f
S
⎞
⎠
⎞
⎠
DS25048B-page 25
3
⎞
⎠
⎞
⎠
100000 1000000
3