TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet
TMP89xy60UG/FG
Specifications of TMP89xy60UG/FG
Related parts for TMP89xy60UG/FG
TMP89xy60UG/FG Summary of contents
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Bit Microcontroller TLCS-870/C1 Series TMP89FS60 ...
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... TOSHIBA CORPORATION All Rights Reserved ...
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Precaution for Using the Emulation Chip (Development Tool) ・ Precaution for debugging the voltage detection circuit In debug using the RTE870/C1 In-Circuit Emulator (ICE mode) with the TMP89C900 mounted on it, no interrupt is generated when the supply voltage rises ...
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TMP89FS60 ...
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Date Revision 2007/10/27 1 2007/11/2 2 2008/2/19 3 2008/9/4 4 2009/7/23 5 Revision History First Release Contents Revised Contents Revised Contents Revised Contents Revised ...
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...
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Table of Contents Precaution for Using the Emulation Chip (Development Tool) TMP89FS60 1.1 Features......................................................................................................................................1 1.2 Pin Assignment..........................................................................................................................3 1.3 Block Diagram...........................................................................................................................4 1.4 Pin Names and Functions..........................................................................................................5 2. CPU Core 2.1 Configuration.............................................................................................................................9 2.2 Memory space............................................................................................................................9 2.2.1 Code area.............................................................................................................................................................................9 2.2.1.1 RAM 2.2.1.2 BOOTROM ...
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Internal factor reset detection status register 2.4.4.9 How to use the external reset input pin as a port 2.5 Revision History......................................................................................................................46 3. Interrupt Control Circuit 3.1 Configuration...........................................................................................................................49 3.2 Interrupt Latches (IL27 to IL3)................................................................................................50 3.3 Interrupt Enable Register (EIR)...............................................................................................51 3.3.1 ...
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Power-on Reset Circuit 6.1 Configuration...........................................................................................................................81 6.2 Function...................................................................................................................................81 7. Voltage Detection Circuit 7.1 Configuration...........................................................................................................................83 7.2 Control.....................................................................................................................................84 7.3 Function...................................................................................................................................85 7.3.1 Enabling/disabling the voltage detection operation...........................................................................................................85 7.3.2 Selecting the voltage detection operation mode................................................................................................................85 7.3.3 Selecting the detection voltage level.................................................................................................................................86 7.3.4 Voltage detection ...
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Divider Output (DVO) 11.1 Configuration.......................................................................................................................137 11.2 Control.................................................................................................................................138 11.3 Function...............................................................................................................................139 11.4 Revision History..................................................................................................................140 12. Time Base Timer (TBT) 12.1 Time Base Timer.................................................................................................................141 12.1.1 Configuration.................................................................................................................................................................141 12.1.2 Control...........................................................................................................................................................................141 12.1.3 Functions........................................................................................................................................................................142 12.2 Revision History..................................................................................................................144 13. 16-bit Timer Counter (TCA) 13.1 Configuration.......................................................................................................................146 13.2 Control.................................................................................................................................147 ...
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Control.................................................................................................................................173 14.2.1 Timer counter 00............................................................................................................................................................173 14.2.2 Timer counter 01............................................................................................................................................................175 14.2.3 Common to timer counters 00 and 01............................................................................................................................177 14.2.4 Operation modes and usable source clocks...................................................................................................................179 14.3 Low Power Consumption Function.....................................................................................180 14.4 Functions..............................................................................................................................181 14.4.1 8-bit timer mode.............................................................................................................................................................181 14.4.1.1 Setting 14.4.1.2 Operation ...
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Transition of TXD pin status.........................................................................................................................................225 16.6 Transfer Data Format...........................................................................................................226 16.7 Infrared Data Format Transfer Mode..................................................................................226 16.8 Transfer Baud Rate..............................................................................................................227 16.8.1 Transfer baud rate calculation method...........................................................................................................................228 16.8.1.1 Bit width adjustment using UART0CR2<RTSEL> 16.8.1.2 Calculation of set values of UART0CR2<RTSEL> and ...
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Free data format.............................................................................................................................................................273 18.2 Configuration.......................................................................................................................274 18.3 Control.................................................................................................................................275 18.4 Functions..............................................................................................................................278 18.4.1 Low Power Consumption Function...............................................................................................................................278 18.4.2 Selecting the slave address match detection and the GENERAL CALL detection.......................................................278 18.4.3 Selecting the number of clocks for data transfer and selecting the acknowledgement ...
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Flash Memory 21.1 Flash Memory Control.........................................................................................................316 21.2 Functions..............................................................................................................................319 21.2.1 Flash memory command sequence execution and toggle control (FLSCR1 <FLSMD>).............................................319 21.2.2 Flash memory area switching (FLSCR1<FAREA>).....................................................................................................320 21.2.3 RAM area switching (SYSCR3<RAREA>)..................................................................................................................322 21.2.4 BOOTROM area switching (FLSCR1<BAREA>).......................................................................................................322 21.2.5 Flash memory standby ...
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Mask ROM emulation setting command (0xD0)..........................................................................................................372 22.8.9 Flash memory security setting command (0xFA)..........................................................................................................373 22.9 Error Code...........................................................................................................................374 22.10 Checksum (SUM)..............................................................................................................375 22.10.1 Calculation method......................................................................................................................................................375 22.10.2 Calculation data...........................................................................................................................................................375 22.11 Intel Hex Format (Binary).................................................................................................376 22.12 Security..............................................................................................................................377 22.12.1 Passwords.....................................................................................................................................................................377 22.12.1.1 How a password can ...
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MCU mode (Flash programming or erasing)................................................................................................................408 25.7.2 MCU mode (Except Flash Programming or erasing)....................................................................................................408 25.7.3 Serial PROM mode........................................................................................................................................................409 25.8 Flash Characteristics ...........................................................................................................410 25.8.1 Write characteristics......................................................................................................................................................410 25.9 Oscillating Condition...........................................................................................................411 25.10 Handling Precaution..........................................................................................................411 25.11 Revision History................................................................................................................412 26. Package Dimensions x ...
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The TMP89FS60 is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 61440 bytes of Flash Memory. Product No. TMP89FS60UG TMP89FS60FG Note : * ; Under development 1.1 Features 1. 8-bit single chip microcomputer TLCS-870/C1 series - Instruction execution time : ...
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Features - Trace - RAM monitor - Flash memory writing 18. Clock operation mode control circuit : 2 circuit Single clock mode / Dual clock mode 19. Low power consumption operation (8 mode) - STOP mode: Oscillation stops. (Battery/Capacitor ...
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Pin Assignment P82 P83 P84 (SO1/TXD1) P90 (SI1/RXD1) P91 (SCLK1) P92 (TXD2) P93 (RXD2) P94 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 RA000 Figure 1-1 Pin Assignment Page 3 TMP89FS60 P51 (AIN9) P50 (AIN8) P47 (AIN7/KWI7) P46 (AIN6/KWI6) ...
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Block Diagram 1.3 Block Diagram RA000 Figure 1-2 Block Diagram Page 4 TMP89FS60 ...
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Pin Names and Functions The TMP89FS60 has MCU mode, parallel PROM mode, and serial PROM mode. Table 1-1 shows the pin functions in MCU mode. The serial PROM mode is explained later in a separate chapter. Table 1-1 Pin ...
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Pin Names and Functions Table 1-2 Pin Names and Functions (2/4) Pin Name P47 AIN7 KWI7 P46 AIN6 KWI6 P45 AIN5 KWI5 P44 AIN4 KWI4 P43 AIN3 KWI3 P42 AIN2 KWI2 P41 AIN1 KWI1 P40 AIN0 KWI0 P57 AIN15 ...
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Table 1-2 Pin Names and Functions (3/4) Pin Name P76 INT3 P75 INT2 P74 DVO P73 TCA1 PPGA1 P72 TCA0 PPGA0 P71 TC01 PPG01 PWM01 P70 TC00 PPG00 PWM00 P84 P83 P82 P81 TC03 PPG03 PWM03 P80 TC02 PPG02 PWM02 ...
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Pin Names and Functions Table 1-2 Pin Names and Functions (4/4) Pin Name P90 TXD1 SO1 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 MODE VAREF AVDD AVSS VDD VSS RA000 Input/Output Functions IO PORT90 O UART data output ...
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CPU Core 2.1 Configuration The CPU core consists of a CPU, a system clock controller and a reset circuit. This chapter describes the CPU core address space, the system clock controller and the reset circuit. 2.2 Memory space The ...
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Memory space 2.2.1.1 RAM The RAM is mapped in the data area immediately after reset release. By setting SYSCR3<RAREA> to "1" and writing 0xD4 to SYSCR4, RAM can be mapped to 0x0040to 0x0C3F in the code area to execute ...
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Note 3: After IRSTSR<FCLR> is modified, SYSCR4 should be written 0x71 (Enable code for IRSTSR<FCLR> in NORMAL mode when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, IRSTSR<FCLR> may be enabled at unexpected timing. System control status register 4 7 SYSSR4 (0x0FDF) Bit ...
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Memory space Flash memory control register 1 FLSCR1 (0x0FD0) Bit Symbol Read/Write After reset Specifies mapping of the BOOT- BAREA ROM in the code and data areas Note:The flash memory control register 1 has a double-buffer structure comprised of ...
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Data area The data area stores the data to be accessed as sources and destinations of transfer and calculation instructions. The SFR, the RAM, the BOOTROM and the FLASH are mapped in the data area. Figure 2-2 Memory Map ...
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Memory space Example: RAM initialization program CLR_RAM: LD INC DEC J 2.2.2.3 BOOTROM The BOOTROM is not mapped in the code area or the data area after reset release. Setting FLSCR1<BAREA> to "1" and writing 0xD5 ...
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System clock controller 2.3.1 Configuration The system clock controller consists of a clock generator, a clock gear, a timing generator, a warm-up counter and an operation mode control circuit. Clock generator XIN High-frequency clock oscillation circuit XOUT XTIN Low-frequency ...
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System clock controller Note 3: If the STOP mode is activated with SYSCR1<OUTEN> set at "0", the port internal input is fixed to "0". Therefore, an external interrupt may be set at the falling edge, depending on the pin ...
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Note 4: Before starting the warm-up counter operation, set the source clock and the frequency division rate at WUCCR and set the warm-up time at WUCDR. Warm-up counter data register 7 WUCDR (0x0FCE) Bit Symbol Read/Write After reset 0 WUCDR ...
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System clock controller Enabling/disabling the oscillation of the high-frequency clock oscillation circuit and the low-frequency clock oscillation circuit and switching the pin function to ports are controlled by the software and hardware. The software control is executed by SYSCR2<XEN>, ...
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The gear clock (fcgck) may be longer than the set clock width, immediately after CGCR<FCGCKSEL> is changed. Immediately after reset release, the gear clock (fcgck) becomes the clock that is a quarter of the high- frequency clock (fc). Table 2-2 ...
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System clock controller 2. Prescaler and divider 3. Machine cycle 2.3.4 Warm-up counter The warm-up counter is a circuit that counts the high-frequency clock (fc) and the low-frequency clock (fs), and it consists of a source clock selection circuit, ...
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Warm-up counter operation when the oscillation is enabled by the hardware (1) When a power-on reset is released or a reset is released The warm-up counter serves to secure the time after a power-on reset is released before the ...
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System clock controller Note 2: The clock output from the oscillation circuit is used as the input clock to the warm-up counter. The warm-up time contains errors because the oscillation frequency is unstable until the oscillation circuit becomes stable. ...
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Single-clock mode Only the gear clock (fcgck) is used for the operation in the single-clock mode. The main system clock (fm) is generated from the gear clock (fcgck). Therefore, the machine cycle time is 1/fcgck [s]. The gear clock ...
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System clock controller When the IMF is "0" or when the IMF is "1" and the EF5 (the individual interrupt enable flag for the time base timer) is "0", the operation is restarted by the instruction that follows the ...
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The IDLE2 mode can be activated and released in the same way as for the IDLE1 mode. The operation returns to the NORMAL2 mode after this mode is released. (5) SLEEP1 mode In this mode, the high-frequency clock oscillation circuit ...
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System clock controller 2.3.5.4 Transition of operation modes IDLE0 mode (a) Single-clock mode IDLE2 mode SLEEP1 mode (b) Dual-clock mode Note 1: The NORMAL1 and NORMAL2 modes are generically called the NORMAL mode; the SLOW1 and SLOW2 modes are ...
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Table 2-3 Operation Modes and Conditions Oscillation circuit Operation mode High-fre- quency RESET NORMAL1 Oscillation Single clock IDLE1 IDLE0 STOP Stop NORMAL2 IDLE2 Oscillation SLOW2 Dual clock SLOW1 Stop SLEEP1 SLEEP0 STOP 2.3.6 Operation Mode Control 2.3.6.1 STOP mode The ...
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System clock controller Note:During the STOP period (from the start of the STOP mode to the end of the warm-up), due to 1. Release by the STOP pin Example: Starting the STOP mode from NORMAL mode after testing P00 ...
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Note: When the STOP mode is released, the warm-up counter source clock automatically changes to the clock that generated the main system clock when the STOP mode was started, regardless of WUCCR<WUCSEL>. STOP pin XOUT pin NORMAL mode Note: Even ...
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System clock controller 3. Release by the voltage detection circuits (3) STOP mode release operation The STOP mode is released in the following sequence: 1. Oscillation starts. For the oscillation start operation in each mode, refer to "Table 2-4 ...
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Note:When the operation returns to the NORMAL2 mode input to the frequency division circuit of the warm-up counter. 2.3.6.2 IDLE1/2 and SLEEP1 modes The IDLE1/2 and SLEEP1 modes are controlled by the system control register 2 (SYSCR2) and ...
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System clock controller (1) Start the IDLE1/2 and SLEEP1 modes After the interrupt master enable flag (IMF) is set to "0", set the individual interrupt enable flag (EF) to "1", which releases IDLE1/2 and SLEEP1 modes. To start the ...
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Figure 2-11 IDLE0 and SLEEP0 Modes ・ Start the IDLE0 and SLEEP0 modes Stop (disable) the peripherals such as a timer counter. To start the IDLE0 or SLEEP0 mode, set SYSCR2<TGHALT> to "1". ・ Release the IDLE0 ...
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System clock controller (1) Normal release mode (IMF, EF5, TBTCR<TBTEN> = "0") The IDLE0 or SLEEP0 mode is released when the falling edge of the source clock selected at TBTCR<TBTCK> is detected. After the IDLE0 or SLEEP0 mode is ...
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Quarter of the low-frequency clock (fs/4) Gear clock (fcgck) SYSCR2<SYSCK> Main system clock Figure 2-12 Switching of the Main System Clock (fm) (Switching from fcgck to fs/4) Example 1: Switching from the NORMAL2 mode to the SLOW1 mode (when fc ...
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System clock controller VINTWUC: DW (2) Switching from the SLOW1 mode to the NORMAL1 mode Set SYSCR2<XEN> to "1" to enable the high-frequency clock (fc) to oscillate. Confirm at the warm- up counter that the oscillation of the basic ...
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SET (EIRL). 4 SET (SYSCR2) .6 ¦ ; #### Interrupt service routine of warm-up counter interrupts #### PINTWUC: CLR (SYSCR2). 4 NOP NOP CLR (SYSCR2). 5 RETI ¦ VINTWUC: DW PINTWUC RB000 ;Enables INTWUC interrupts ;SYSCR2<XEN> ;(Starts the ...
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Reset Control Circuit 2.4 Reset Control Circuit The reset circuit controls the external and internal factor resets and initializes the system. 2.4.1 Configuration The reset control circuit consists of the following reset signal generation circuits: 1. External reset input ...
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Note 3: After SYSCR3<RSTDIS> is modified, SYSCR4 should be written 0xB2 (Enable code for SYSCR3<RSTDIS>) in NOR- MAL1 mode when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, SYSCR3<RSTDIS> may be enabled at unexpec- ted timing. Note 4: Bits ...
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Reset Control Circuit Internal factor reset detection status register IRSTSR (0x0FCC) Bit Symbol Read/Write After reset FCLR Flag initialization control FLSRF Flash standby reset detection flag TRMDS Trimming data status TRMRF Trimming data reset detection flag Voltage detection reset ...
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Table 2-5 Initialization of Built-in Hardware by Reset Operation and Its Status after Release Built-in hardware Program counter (PC) Stack pointer (SP) RAM General-purpose registers ( and IY) Register bank selector (RBS) ...
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Reset Control Circuit 2.4.4 Reset Signal Generating Factors Reset signals are generated by each factor as follows: 2.4.4.1 Power-on reset The power-on reset is an internal reset that occurs when power is turned on. During power-up, a power-on reset ...
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VDD Operating voltage range V PROFF Power-on reset RESET pin CPU and peripheral circuits reset When the supply voltage rises rapidly (When the reset time depends on power-on reset) t VDD Operating voltage range V PROFF Power-on reset RESET ...
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Reset Control Circuit ・ When the supply voltage is within the operating voltage range holding the RESET pin Low for 5 [μs] or longer generates a reset. Then, changing the RESET pin level to High starts a warm-up period. ...
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When IRSTSR<TRMDS> is read as "1" in the initialize routine immediately after reset release, the trim- ming data need to be reloaded by generating an internal factor reset, such as a system clock reset, and activating the warm-up operation again. ...
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Revision History 2.5 Revision History Rev "2.3.4.1 Warm-up counter operation when the oscillation is enabled by the hardware" Fixed specification from T.B.D. to 0x66. RA001 "Figure 2-15 External Reset Input (when the power is turned on)" and "Figure 2-16 ...
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Interrupt Control Circuit The TMP89FS60 has a total of 27 interrupt sources excluding reset. Interrupts can be nested with priorities. Three of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt ...
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Note 1: To use the watchdog timer interrupt (INTWDT), clear WDCTR<WDTOUT> to "0" (It is set for the "Reset request" after reset is released). For details, see "Watchdog Timer". Note 2: Vector address areas can be changed by the SYSCR3<RVCTR> ...
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Configuration interrupts Non-maskable RA003 interrupts Maskable circuit change priority interrupt Maskable Figure 3-1 Interrupt Control Circuit Page 49 TMP89FS60 ...
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Interrupt Latches (IL27 to IL3) 3.2 Interrupt Latches (IL27 to IL3) An interrupt latch is provided for each interrupt source, except for a software interrupt and an undefined instruction execution interrupt. When an interrupt request is generated, the latch ...
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Interrupt Enable Register (EIR) The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (software interrupt, undefined instruction interrupt and watchdog interrupt). Non-maskable interrupts are accepted regardless of the contents of the ...
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Interrupt Enable Register (EIR) Interrupt latch (ILL) ILL (0x0FE0) Bit Symbol Read/Write After reset Function Interrupt latch (ILH) ILH (0x0FE1) Bit Symbol Read/Write After reset Function Interrupt latch (ILE) ILE (0x0FE2) Bit Symbol Read/Write After reset Function Interrupt latch ...
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Interrupt enable register (EIRL) 7 EIRL (0x003A) Bit Symbol EF7 Read/Write R/W After reset 0 INTTXD0 Function Interrupt enable register (EIRH) 7 EIRH (0x003B) Bit Symbol EF15 Read/Write R/W After reset 0 INTSBI0/IN- Function TSIO0 Interrupt enable register (EIRE) EIRE ...
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Maskable Interrupt Priority Change Function 3.4 Maskable Interrupt Priority Change Function The priority of maskable interrupts (IL4 to IL27) can be changed to four levels, Levels regardless of the basic priorities 5 to 28. Interrupt priorities ...
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Interrupt priority change control register 4 ILPRS4 7 (0x0FF3) Bit Symbol Read/Write After reset 0 IL19P Sets the interrupt priority of IL19. IL18P Sets the interrupt priority of IL18. IL17P Sets the interrupt priority of IL17. IL16P Sets the interrupt ...
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Interrupt Sequence 3.5 Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to “0” by resetting or an instruction. Interrupt acceptance sequence requires 8-machine cycles after the completion ...
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A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt is requested in the interrupt service routine. In order to utilize nested interrupt service, the IMF must be set to “1” in ...
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Interrupt Sequence 3.5.3.2 Using data transfer instructions To save only a specific register without nested interrupts, data transfer instructions are available. Example :Save/store register using data transfer instructions PINTxx: LD Interrupt processing LD RETI Figure 3-4 Saving/Restoring General-purpose Registers ...
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Main task The register bank BANK0 is in use. Figure 3-5 Saving/Restoring General-purpose Registers under Interrupt Processing 3.5.4 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows. 1. Program counter (PC) and program status word (register bank) are re- stored ...
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Software Interrupt (INTSW) 3.6 Software Interrupt (INTSW) Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW is the top-priority interrupt). Use the SWI instruction only for address error detection or for debugging described below. ...
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Revision History Rev Revised from WDTCR1<WDTOUT> to WDCTR<WDTOUT> RA003 Added chapter "3.5 Interrupt Sequence" "Figure 3-3 Saving/restoring general-purpose registers" Revised SP position RA003 Description Page 61 TMP89FS60 ...
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Revision History RA003 Page 62 TMP89FS60 ...
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External Interrupt control circuit External interrupts detects the change of the input signal and generates an interrupt request. Noise can be removed by the built-in digital noise canceller. 4.1 Configuration The external interrupt control circuit consists of a noise ...
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Control Low power consumption register 3 POFFCR3 (0x0F77) Bit Symbol Read/Write After reset INT5EN INT5 control INT4EN INT4 control INT3EN INT3 control INT2EN INT2 control INT1EN INT1 control INT0EN INT0 control Note 1: Clearing INTxEN(x "0" ...
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Note 3: Interrupt requests may be generated when EINTCR1 is changed. Before doing such operation, clear the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is changed from NOR- MAL1/2 or IDLE1/2 ...
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Control External interrupt control register 3 EINTCR3 (0x0FDA) Bit Symbol Read/Write After reset Noise canceller pass signal level INI3LVL when the interrupt request signal is generated for external interrupt 3 Selects the interrupt request gener- INT3ES ating condition for ...
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External interrupt control register 4 7 EINTCR4 (0x0FDB) Bit Symbol - Read/Write R After reset 0 Noise canceller pass signal level INI4LVL when the interrupt request signal is generated for external interrupt 4 Selects the interrupt request gener- INT4ES ating ...
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Function Table 4-1 External Interrupts Source Pin Enable conditions INT0 INT0 IMF AND EF16 = 1 Falling edge INT1 INT1 IMF AND EF17 = 1 INT2 INT2 IMF AND EF18 = 1 INT3 INT3 IMF AND EF19 = 1 ...
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External interrupts 1/2/3 External interrupts 1/2/3 detect the falling edge, the rising edge or both edges of the INT1, INT2 and INT3 pins and generate interrupt request signals. 4.3.3.1 Interrupt request signal generating condition detection function Select interrupt request ...
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Function Signal after noise removal In SLOW1/2 or SLEEP1 mode, a signal is sampled by the low frequency clock divided the same level is detected twice consecutively, the signal is recognized as a signal. In IDLE0, ...
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A noise canceller pass signal monitoring function when interrupt request signals are generated The level of a signal that has passed through the noise canceller when an interrupt request is generated can be read by using EINTCR4<INT4LVL>. When both ...
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Function Signal after noise removal In SLOW1/2 or SLEEP1 mode, a signal is sampled by the low frequency clock divided the same level is detected twice consecutively, the signal is recognized as a signal. In IDLE0, ...
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Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the CPU to a system recovery routine. The watchdog ...
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Control 5.2 Control The watchdog timer is controlled by the watchdog timer control register (WDCTR), the watchdog timer control code register (WDCDR), the watchdog timer counter monitor (WDCNT) and the watchdog timer status (WDST). The watchdog timer is enabled ...
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Note:WDCDR is a write-only register and must not be accessed by using a read-modify-write instruction, such as a bit operation. 8-bit up counter monitor 7 WDCNT (0x0FD6) Bit Symbol Read/Write After reset 0 Monitors the count value of the 8-bit ...
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Functions 5.3 Functions The watchdog timer can detect the CPU malfunctions and deadlock by detecting the overflow of the 8-bit up counter and detecting releasing of the 8-bit up counter outside the clear time. The watchdog timer stoppage and ...
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When WDCTR<WDTW> is “00” When WDCTR<WDTW> is “01” When WDCTR<WDTW> is “10” When WDCTR<WDTW> is “11” Figure 5-3 WDCTR<WDTW> and the 8-bit up Counter Clear Time 5.3.3 Setting the overflow time of the ...
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Functions 2. When the watchdog timer reset request signal is selected (when WDCTR<WDTOUT> is "1") Setting WDCTR<WDTOUT> to "1" causes a watchdog timer reset request signal to occur when the 8-bit up counter overflows. This watchdog timer reset request ...
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WDST<WINTST1> is set to "1" when a watchdog timer interrupt request signal occurs due to the operation for releasing the 8-bit up counter outside the clear time. You can know which factor has caused a watchdog timer interrupt request signal ...
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Functions RA000 Page 80 TMP89FS60 ...
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Power-on Reset Circuit The power-on reset circuit generates a reset when the power is turned on. When the supply voltage is lower than the detection voltage of the power-on reset circuit, a power-on reset signal is generated. 6.1 Configuration ...
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Function Supply voltage (VDD) Operating voltage VPROFF VPRON Power-on reset signal Warm-up counter clock CPU/peripheral circuits reset signal Note 1: The power-on reset circuit may operate improperly, depending on fluctuations in the supply voltage (VDD). Refer to the electrical ...
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Voltage Detection Circuit The voltage detection circuit detects any decrease in the supply voltage and generates INTVLTD interrupt request signals and voltage detection reset signals. Note:The voltage detection circuit may operate improperly, depending on fluctuations in the supply voltage ...
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Control 7.2 Control The voltage detection circuit is controlled by voltage detection control registers 1 and 2. Voltage detection control register 1 VDCR1 (0x0FC6) Bit Symbol Read/Write After reset Voltage detection 2 flag (Retains the VD2F state when VDD<VD2LVL ...
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Function Two detection voltages (VDxLVL can be set in the voltage detection circuit. For each voltage, enabling/ disabling the voltage detection and the operation to be executed when the supply voltage (VDD) falls to ...
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Function VDCR1 and VDCR2 are initialized by a power-on reset or an external reset input only. A voltage detection reset signal is generated continuously as long as the supply voltage (VDD) is lower than the detection voltage (VDxLVL). Detection ...
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VDD level Detection voltage level VDCR2<VDxEN> VDCR1<VDxF> VDCR1<VDxSF> Figure 7-4 Changes in the Voltage Detection Flag and the Voltage Detection Status Flag RB000 Write "0" to VDCR1<VDxF> The flag is not set because VDCR2<VDxEN> is "0" Page 87 TMP89FS60 ...
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Register Settings 7.4 Register Settings 7.4.1 Setting procedure when the operation mode is set to generate INTVLTD interrupt request signals When the operation mode is set to generate INTVLTD interrupt request signal, make the following setting: 1. Clear the ...
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Clear VDCR2<VDxMOD> to "0" to set the operation mode to generate INTVLTD interrupt request signals. 3. Clear VDCR2<VDxEN> to "0" to disable the voltage detection operation. Note:If the voltage detection circuit is disabled without clearing interrupt enable flag, unexpected ...
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Revision History 7.5 Revision History Rev RA001 " Voltage detection control register 1" Revised VD1LVL and VD2LVL. RA002 Revised from VDCR2<VDxLVL> to VDCR1<VDxLVL> "7.4.1 Setting procedure when the operation mode is set to generate INTVLTD interrupt request signals" Added ...
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I/O Ports The TMP89FS60 has 9 parallel input/output ports (58 pins) as follows: Table 8-1 List of I/O Ports Port name Pin name Number of pins P03 to P00 Port P0 (Note) Port P1 P13 to P10 Port P2 ...
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Each output port contains a latch, which holds the output data. No input port has a latch, so the external input data should be externally held until the input data is read from outside or reading should be performed several ...
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I/O Port Control Registers The following control registers are used for I/O ports. (The port number is indicated in place of x.) Registers that can be set vary depending on the port. For details, refer to the description of ...
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List of I/O Port Settings 8.2 List of I/O Port Settings For the setting methods for individual I/O ports, refer to the following table. Table 8-2 List of I/O Port Settings Port name Pin name Port P0 P03 to ...
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Table 8-2 List of I/O Port Settings Port name Pin name Port P7 P77 to P70 P77 P76 P75 P74 P73 P72 P71 PPG01 / PWM01 output P70 PPG00 / PWM00 output Port P8 P84 to P80 P81 PPG03 / ...
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List of I/O Port Settings RA007 Symbol and nu- Meaning meric characters 0 Set "0". 1 Set "1". Don’t care * (Operation is the same whether "1" or "0" is selected.) The sink open drain output or the C-MOS ...
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I/O Port Registers 8.3.1 Port P0 (P03 to P00) Port 4-bit input/output port that can be set to input or output for each bit individually, and it is also used as the high-frequency oscillation connection pin ...
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I/O Port Registers Pull-up control (for each bit) P0PU2 write Input/output control (for each bit) P0CR2 write Function control (for each bit) P0FC2 write Output latch (for each bit) P0DR2 write P0PRD2 read Pull-up control (for each bit) P0PU3 ...
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Port P0 output latch 7 P0DR (0x0000) Bit Symbol - Read/Write R After reset 0 0: Function 1: Port P0 input/output control 7 P0CR (0x0F1A) Bit Symbol - Read/Write R After reset 0 0: Function 1: Note:P0CR1 and P0CR0 must ...
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I/O Port Registers Port P0 input data P0PRD (0x000D) Bit Symbol Read/Write After reset Function Note Don’t care Note Note Don’t care Note ...
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Port P1 (P13 to P10) Port 4-bit input/output port that can be set to input or output for each bit individually, and is also used as the external interrupt input, the STOP mode release signal input ...
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I/O Port Registers P1PRD read SYSCR3<RSTDIS> Power-on reset signal Reset 1 Reset 2 Low-voltage detection reset 1 signal Low-voltage detection reset 2 signal Watchdog timer reset signal System clock reset signal Trimming data reset signal Flash standby reset signal ...
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Port P1 output latch 7 P1DR (0x0001) Bit Symbol - Read/Write R After reset 0 0: Function 1: Port P1 input/output control 7 P1CR (0x0F1B) Bit Symbol - Read/Write R After reset 0 0: Function 1: Note:Symbol "I" means secondary ...
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I/O Port Registers Note RA007 Page 104 TMP89FS60 ...
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Port P2 (P27 to P20) Port 8-bit input/output port that can be set to input or output for each bit individually, and it is also used as the serial bus interface input/output, the serial interface input/output, ...
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I/O Port Registers Peripheral functions SIO0 UART0 P2PRD read Peripheral functions SIO0 P2PRD read I2C0 RA007 Pull-up control (for each bit) P2PU write Output control (for each bit) P2OUTCR write Input/output control (for each bit) P2CR write Function control ...
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Port P2 output latch 7 P2DR (0x0002) Bit Symbol P27 Read/Write R/W After reset 0 0: Outputs L level when the output mode is selected. Function Outputs H level when the output mode is selected. (Serves as Hi-Z or pull-up ...
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I/O Port Registers Port P2 function control P2FC (0x0F36) Bit Symbol Read/Write After reset 0: Function 1: Port P2 output control P2OUTCR (0x0F43) Bit Symbol Read/Write After reset 0: Function 1: Port P2 built-in pull-up resistor control P2PU (0x0F29) ...
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Port P4 (P47 to P40) Port 8-bit input/output port that can be set to input or output for each bit individually, and it is also used as the analog input and the key-on wakeup input. Port ...
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I/O Port Registers Port P4 output latch P4DR (0x0004) Bit Symbol Read/Write After reset 0: Function 1: Port P4 input/output control P4CR (0x0F1E) Bit Symbol Read/Write After reset 0: Function 1: Note 1: Symbol "I" means secondary function input. ...
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Table 8-11 P4PRD Read Value Note Don’t care Note RA007 Set condition P4PRDi read value P4CRi P4FCi 0 0 Contents of port * 1 "0" "0" Page 111 TMP89FS60 ...
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I/O Port Registers 8.3.5 Port P5 (P57 to P50) Port 8-bit input/output port that can be set to input or output for each bit individually, and it is also used as the analog input. Table 8-12 ...
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Port P5 output latch 7 P5DR (0x0005) Bit Symbol P57 Read/Write R/W After reset 0 0: Outputs L level when the output mode is selected Function 1: Outputs H level when the output mode is selected. Port P5 input/output control ...
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I/O Port Registers 8.3.6 Port P7 (P77 to P70) Port 8-bit input/output port that can be set to input or output for each bit individually, and it is also used as the external interrupt input, the ...
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Port P7 output latch 7 P7DR (0x0007) Bit Symbol P77 Read/Write R/W After reset 0 0: Outputs L level when the output mode is selected Function 1: Outputs H level when the output mode is selected Port P7 input/output control ...
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I/O Port Registers 8.3.7 Port P8 (P84 to P80) Port 5-bit input/output port that can be set to input or output for each bit individually, and it is also used as the timer counter input/output. Table ...
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Port P8 output latch 7 P8DR (0x0008) Bit Symbol - Read/Write R After reset 0 0: Function 1: Port P8 input/output control 7 P8CR (0x0F22) Bit Symbol - Read/Write R After reset 0 0: Function 1: Note:Symbol "I" means secondary ...
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I/O Port Registers 8.3.8 Port P9 (P94 to P90) Port 5-bit input/output port that can be set to input or output for each bit individually, and it is also used as the serial interface and the ...
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Port P9 output latch 7 P9DR (0x0009) Bit Symbol - Read/Write R After reset 0 0: Function 1: Port P9 input/output control 7 P9CR (0x0F23) Bit Symbol - Read/Write R After reset 0 0: Function 1: Note:Symbol "I" means secondary ...
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I/O Port Registers Port P9 function control P9FC (0x0F3D) Bit Symbol Read/Write After reset 0: Function 1: Port P9 output control P9OUTCR (0x0F4A) Bit Symbol Read/Write After reset 0: Function 1: Port P9 built-in pull-up resistor control P9PU (0x0F30) ...
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Port PB (PB7 to PB0) Port 8-bit input/output port that can be set to input or output for each bit individually. Table 8-20 Port PB PB7 Secondary - function Input/output control (for each bit) PBCR write ...
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I/O Port Registers Port PB output latch PBDR (0x000B) Bit Symbol Read/Write After reset 0: Function 1: Port PB input/output control PBCR (0x0F25) Bit Symbol Read/Write After reset 0: Function 1: Port PB input data PBPRD (0x0018) Bit Symbol ...
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Serial Interface Selecting Function On the TMP89FS60, the built-in serial interface (SIO, UART and I assignment can be changed. Two out of three functions, SIO0, UART0 and I2C0, can be used at the same time by using this selecting ...
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Serial Interface Selecting Function Serial interface selection control register SERSEL (0x0FCB) Bit Symbol Read/Write After reset 16-bit timer counter A0 input switch- TCA0SEL ing SRSEL1 Serial interface selection 1 SRSEL0 Serial interface selection 0 Note 1: The operation for ...
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Revision History Rev "8.3.13 Port PB (PB75 to PB04)" Added detail description about PB port. " Serial interface selection control register" Deleted SRSEL1. Revised SRSEL2 description from "output" to "input/output". RA002 "Table 8-2 List of I/O Port Settings" Revised ...
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Revision History RA007 Page 126 TMP89FS60 ...
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Special Function Registers The TMP89FS60 adopts the memory mapped I/O system, and all peripheral hardware data control and transfer operations are performed through the special function registers (SFR). SFR1 is mapped on addresses 0x0000 to 0x003F, SFR2 is mapped ...
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SFR2 (0x0F00 to 0x0FFF) 9.2 SFR2 (0x0F00 to 0x0FFF) Table 9-2 SFR2 (0x0F00 to 0x0F7F) Address Register Name 0x0F00 Reserved 0x0F01 Reserved 0x0F02 Reserved 0x0F03 Reserved 0x0F04 Reserved 0x0F05 Reserved 0x0F06 Reserved 0x0F07 Reserved 0x0F08 Reserved 0x0F09 Reserved 0x0F0A ...
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Table 9-3 SFR2 (0x0F80 to 0x0FFF) Address Register Name Address 0x0F80 Reserved 0x0FA0 0x0F81 Reserved 0x0FA1 0x0F82 Reserved 0x0FA2 0x0F83 Reserved 0x0FA3 0x0F84 Reserved 0x0FA4 0x0F85 Reserved 0x0FA5 0x0F86 Reserved 0x0FA6 0x0F87 Reserved 0x0FA7 0x0F88 T02REG 0x0FA8 0x0F89 T03REG 0x0FA9 ...
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SFR3 (0x0E40 to 0x0EFF) 9.3 SFR3 (0x0E40 to 0x0EFF) Table 9-4 SFR3 (0x0E40 to 0x0EBF) Address Register Name 0x0E40 Reserved 0x0E41 Reserved 0x0E42 Reserved 0x0E43 Reserved 0x0E44 Reserved 0x0E45 Reserved 0x0E46 Reserved 0x0E47 Reserved 0x0E48 Reserved 0x0E49 Reserved 0x0E4A ...
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Table 9-5 SFR3 (0x0EC0 to 0x0EFF) Address Register Name Address 0x0EC0 Reserved 0x0ED0 0x0EC1 Reserved 0x0ED1 0x0EC2 Reserved 0x0ED2 0x0EC3 Reserved 0x0ED3 0x0EC4 Reserved 0x0ED4 0x0EC5 Reserved 0x0ED5 0x0EC6 Reserved 0x0ED6 0x0EC7 Reserved 0x0ED7 0x0EC8 Reserved 0x0ED8 0x0EC9 Reserved 0x0ED9 ...
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SFR3 (0x0E40 to 0x0EFF) RA001 Page 132 TMP89FS60 ...
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Low Power Consumption Function for Peripherals The TMP89FS60 has low power consumption registers (POFFCRn) that save power when specific peripheral functions are unused. Each bit of the low power consumption registers can be set to enable or disable each ...
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Control 10.1 Control The low power consumption function is controlled by the low power consumption registers (POFFCRn Low power consumption register 0 POFFCR0 (0x0F74) Bit Symbol Read/Write After reset TC023EN TC02, 03 control ...
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Low power consumption register 3 POFFCR3 7 (0x0F77) Bit Symbol - Read/Write R/W After reset 0 INT5EN INT5 control INT4EN INT4 control INT3EN INT3 control INT2EN INT2 control INT1EN INT1 control INT0EN INT0 control RA001 ...
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Control RA001 Page 136 TMP89FS60 ...
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Divider Output (DVO) This function outputs approximately 50% duty pulses that can be used to drive the piezoelectric buzzer or other device. 11.1 Configuration RA001 Selector 12 5 fcgck fcgck ...
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Control 11.2 Control The divider output is controlled by the divider output control register (DVOCR). Divider output control register DVOCR (0x0038) Bit Symbol Read/Write After reset Enables/disables DVOEN the divider output Selects the divider output frequency DVOCK Unit: [Hz] ...
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Function Select the divider output frequency at DVOCR<DVOCK>. The divider output is enabled by setting DVOCR<DVOEN> to "1". Then, The rectangular waves selected by DVOCR<DVOCK> is output from DVO pin disabled by clearing DVOVR<DVOEN> to "0". And ...
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Revision History 11.4 Revision History Rev RA001 Deleted SLEEP2 description. RA001 Description Page 140 TMP89FS60 ...
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Time Base Timer (TBT) The time base timer generates the time base for key scanning, dynamic display and other processes. It also provides a time base timer interrupt (INTTBT certain cycle. 12.1 Time Base Timer 12.1.1 Configuration ...
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Time Base Timer Note 4: When SYSCR1<DV9CK> is "1" in the NORMAL 1/2 or IDLE1/2 mode, the interrupt request is subject to some fluctuations to synchronize fs and fcgck. Note 5: Bits TBTCR are read ...
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Example:Set the time base timer interrupt frequency to fcgck/2 DI SET (EIRL (TBTCR), 0y00000010 LD (TBTCR), 0y00001010 RA001 15 [Hz] and enable interrupts. ;IMF ← 0 ;Set the interrupt enable register ;IMF ← 1 ;Set the interrupt ...
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Revision History 12.2 Revision History Rev RA001 Deleted SLEEP2 description RA001 Description Page 144 TMP89FS60 ...
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Timer Counter (TCA) The TMP89FS60 contains 2 channels of high-performance 16-bit timer counters (TCA). This chapter describes the 16-bit timer counter A0. For the 16-bit timer counter A1, replace the SFR addresses and pin names, as shown in ...
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Configuration 13.1 Configuration RB002 Figure 13-1 Timer Counter A0 Page 146 TMP89FS60 TA0OVF TA0CPFA TA0CPFB TA0MPPG TA0TFF TA0S TA0CAP TA0OVE TA0NC TA0METT TA0TED TA0DBE TA0M TA0CK ...
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Control Timer Counter A0 is controlled by the low power consumption register (POFFCR0), the timer counter A0 mode register (TA0MOD), the timer counter A0 control register (TA0CR) and two 16-bit timer A0 registers (TA0DRA and TA0DRB). Low power consumption ...
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Control Timer counter A0 mode register TA0MOD (0x0031) Bit Symbol Read/Write After reset TA0DBE Double buffer control TA0TED External trigger input selection Pulse width measurement mode TA0MCAP control TA0METT External trigger timer mode control Timer counter 1 source clock ...
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Timer counter A0 control register 7 TA0CR (0x0032) Bit Symbol TA0OVE Read/Write R/W After reset 0 TA0OVE Overflow interrupt control TA0TFF Timer F/F control Noise canceller sampling interval TA0NC setting TA0ACAP Auto capture function TA0MPPG PPG output control TA0S Timer ...
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Control Timer counter A0 status register TA0SR (0x0033) Bit Symbol Read/Write After reset TA0OVF Overflow flag TA0CPFA Capture completion flag A TA0CPFB Capture completion flag B Note 1: TA0OVF, TA0CPFA and TA0CPFB are cleared to "0" automatically after TA0SR ...
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Timer counter A0 register AH 15 TA0DRAH (0x002E) Bit Symbol Read/Write After reset 1 Timer counter A0 register AL TA0DRAL 7 (0x002D) Bit Symbol Read/Write After reset 1 Timer counter A0 register BH 15 TA0DRBH (0x0030) Bit Symbol Read/Write After ...
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Low Power Consumption Function 13.3 Low Power Consumption Function Timer counter A0 has the low power consumption register (POFFCR0) that saves power consumption when the timer is not used. Setting POFFCR0<TCA0EN> to "0" disables the basic clock supply to ...
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Timer Function Timer counter A0 has six types of operation modes; timer, external trigger timer, event counter, window, pulse width measurement and programmable pulse generate (PPG) output modes. 13.4.1 Timer mode In the timer mode, the up-counter counts up ...
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Timer Function 13.4.1.4 Register buffer configuration (1) Temporary buffer The TMP89FS60 contains an 8-bit temporary buffer. When a write instruction is executed on TA0DRAL, the data is first stored into this temporary buffer, whether the double buffer is enabled ...
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TA0CR<TA0S> TA0MOD<TA0DBE> Source clock Counter Write to TA0DRAL Write n Write to TA0DRAH Write m Temporary buffer n (8 bits) TA0DRAL n TA0DRAH m INTTCA0 interrupt request Reflected by writing to TA0DRAH TA0CR<TA0S> TA0MOD<TA0DBE> Source clock Counter Write to TA0DRAL ...
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Timer Function TA0CR<TA0S> TA0MOD<TA0ACAP> Source clock Counter TA0DRBL TA0DRBH Read TA0DRBL Read TA0DRBH Read value 00H Figure 13-3 Timer Mode Timing Chart (Auto Capture) RB002 Timer start 0000 0001 0002 18FD 18FE 18FF 1900 1901 1902 1903 1904 1905 ...
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External trigger timer mode In the external trigger timer mode, the up counter starts counting when it is triggered by the input to the TCA0 pin. 13.4.2.1 Setting Setting the operation mode selection TA0MOD<TA0M> to "100" activates the external ...
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Timer Function TA0CR<TA0S> TA0MOD<TA0TED> TCA0 pin input Source clock Counter Write to TA0DRAL Write n Write to TA0DRAH Write m TA0DRAL TA0DRAH INTTCA0 interrupt request TA0CR<TA0S> TA0MOD<TA0TED> TCA0 pin input Source clock Counter Write to TA0DRAL Write n Write ...
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Event counter mode In the event counter mode, the up counter counts up at the edge of the input to the TCA0 pin. 13.4.3.1 Setting Setting the operation mode selection TA0MOD<TA0M> to "010" activates the event counter mode. Set ...
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Timer Function TA0CR<TA0S> TCA0 pin input Counter Write to TA0DRAL Write to TA0DRAH TA0DRAL TA0DRAH INTTCA0 interrupt request RB002 Timer start mn-1 0 Counter clear Write n Write m n Match detection m ...
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Window mode In the window mode, the up counter counts up at the rising edge of the pulse that is logical anded product of the input pulse to the TCA0 pin (window pulse) and the internal clock. 13.4.4.1 Setting ...
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Timer Function TA0CR<TA0S> TA0MOD<TA0TED> TCA0 pin input Source clock Counter Write to TA0DRAL Write n Write to TA0DRAH Write m TA0DRAL TA0DRAH INTTCA0 interrupt request RB002 Timer start Count in the period of H level ...
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Pulse width measurement mode In the pulse width measurement mode, the up counter starts counting at the rising/falling edge(s) of the input to the TCA0 pin and measures the input pulse width based on the internal clock. 13.4.5.1 Setting ...
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Timer Function The captured value must be read from TA0DRB (and also from TA0DRA for the double-edge capture) before the next trigger edge is detected. If the captured value is not read, it becomes undefined. TA0DRA and TA0DRB must ...
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Capture process Figure 13-8 shows an example of the capture process for INTTCA0 interrupt subroutine. The capture edge or overflow state can be easily judged by status register (TA0SR). INTTCA0 interrupt subroutin TA0SR read TA0SR 1 <TA0OVF> Overflow 0 ...
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Timer Function 13.4.6 Programmable pulse generate (PPG) mode In the PPG output mode, an arbitrary duty pulse is output by two timer registers. 13.4.6.1 Setting Setting the operation mode selection TA0MOD<TA0M> to "011" activates the PPG output mode. Select ...
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Register buffer configuration (1) Temporary buffer The TMP89FS60 contains an 8-bit temporary buffer. When a write instruction is executed on TA0DRAL (TA0DRBL), the data is first stored into this temporary buffer, whether the double buffer is enabled or disabled. ...
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Timer Function TA0CR<TA0S> TA0MOD<TA0TFF> Source clock Counter Write to TA0DRAL, H Write n Write to TA0DRBL, H Write m TA0DRAL, H TA0DRBL PPG0 pin output Becomes the level set at TA0TFF INTTCA interrupt request when the timer ...
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Noise Canceller The digital noise canceller can be used in the operation modes that use the TCA0 pin. 13.5.1 Setting When the digital noise canceller is used, the input level is sampled at the sampling intervals set at TA0CR<TA0NC>. ...
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Revision History 13.6 Revision History Rev RA001 "Table 13-3 Timer Mode Resolution and Maximum Time Setting" Revised Resolution and Maximum time of TA0MOD<TA0CK>=11. "Figure 13-1 Timer Counter A0" "13.4.5.2 Operation" RB000 "Figure 13-7 Pulse Width Measurement Mode Timing Chart" ...
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Timer Counter (TC0) The TMP89FS60 contains 4 channels of high-performance 8-bit timer counters (TC0). Each timer can be used for time measurement and pulse output with a prescribed width. Two 8-bit timer counters are cascadable to form a ...
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Configuration 14.1 Configuration DBE0 EIN0 TCK0 TFF0 TCM0 RA005 Figure 14-1 8-bit Timer Counters 00 and 01 Page 172 TMP89FS60 OUTAND TC01RUN TCAS TC00RUN TFF1 EIN1 TCK1 DBE1 TCM1 ...
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Control 14.2.1 Timer counter 00 The timer counter 00 is controlled by the timer counter 00 mode register (T00MOD) and two 8-bit timer registers (T00REG and T00PWM). Timer register 00 15 T00REG (0x0026) Bit Symbol Read/Write After reset 1 ...
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Control Timer counter 00 mode register T00MOD (0x002A) Bit Symbol Read/Write After reset TFF0 Timer F/F0 control DBE0 Double buffer control TCK0 Operation clock selection Selection for using external source EIN0 clock TCM0 Operation mode selection Note 1: fcgck: ...
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Timer counter 01 Timer counter 01 is controlled by timer counter 01 mode register (T01MOD) and two 8-bit timer registers (T01REG and T01PWM). Timer register 01 T01REG 15 (0x0027) Bit Symbol Read/Write After reset 1 Timer register 01 T01PWM ...
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Control Timer counter 01 mode register T01MOD (0x002B) Bit Symbol Read/Write After reset TFF1 Timer F/F1 control DBE1 Double buffer control TCK1 Operation clock selection Selection for using external source EIN1 clock TCM1 Operation mode selection Note 1: fcgck: ...
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Common to timer counters 00 and 01 Timer counters 00 and 01 have the low power consumption register (POFFCR0) and timer 00 and 01 control registers in common. Low power consumption register 0 POFFCR0 7 (0x0F74) Bit Symbol - ...
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Control Timer counter 01 control register T001CR (0x002C) Bit Symbol Read/Write After reset OUTAND Timers 00 and 01 output control TCAS Timers 00 and 01 cascade control Timer 01 control T01RUN Timers 00/01 control (16-bit mode) T00RUN Timer 00 ...
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Operation modes and usable source clocks The operations modes of the 8-bit timers and the usable source clocks are listed below. Table 14-3 Operation Modes and Usable Source Clocks (NORMAL1/2 and IDLE1/2 modes) TCK0 000 fcgck/2 11 Operation mode ...
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Low Power Consumption Function 14.3 Low Power Consumption Function Timer counters 00 and 01 have the low power consumption registers (POFFCR0) that save power when the timers are not used. Setting POFFCR0<TC001EN> to "0" disables the basic clock supply ...
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Functions Timer counters TC00 and TC01 have 8-bit modes in which they are used independently and 16-bit modes in which they are cascaded. The 8-bit modes include four operation modes; the 8-bit timer mode, the 8-bit event counter mode, ...
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Functions be longer than the selected time. If the value set to T00REG is equal to the up counter value, the match detection is executed immediately after data is written into T00REG. Therefore, the interrupt request interval may not ...
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T001CR<T00RUN> T00MOD<DBE0> Source clock Counter Write to T00REG Write m T00REG m INTTC00 interrupt request Reflected by writing to T00REG T001CR<T00RUN> T00MOD<DBE0> Source clock Counter Write to T00REG Write m Double buffer m T00REG m Reflected at the same time ...
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Functions 14.4.2 8-bit event counter mode In the 8-bit event counter mode, the up counter counts up at the falling edge of the input to the TC00 or TC01 pin. The operation of TC00 is described below, and the ...