TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 208

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

14.4
Functions
RA005
14.4.4.2
14.4.4.3
When a match between the internal up counter value and the value set to T00PWM is detected, the output of
the PPG0 pin is reversed. When T00MOD<TFF0> is "0", the PPG0 pin changes from the "L" to "H" level.
When T00MOD<TFF0> is "1", the PPG0 pin changes from the "H" to "L" level.
T00REG is detected, the output of the PPG0 pin is reversed again. When T00MOD<TFF0> is "0", the
PPG0 pin changes from the "H" to "L" level. When T00MOD<TFF0> is "1", the PPG0 pin changes from the
"L" to "H" level. At this time, an INTTC00 interrupt request is generated.
"0x00". The PPG0 pin returns to the level selected at T00MOD<TFF0>.
is disabled by setting T00MOD<DBE0> to "0" or enabled by setting T00MOD<DBE0> to "1".
Setting T001CR<T00RUN> to "1" allows the up counter to increment based on the selected source clock.
Subsequently, the up counter continues counting up. When a match between the up counter value and
When T001CR<T00RUN> is set to "0" during the operation, the up counter is stopped and cleared to
The double buffer can be used for T00PWM and T00REG by setting T00MOD<DBE0>. The double buffer
Operation
Double buffer
・ When the double buffer is enabled
・ When the double buffer is disabled
set value is first stored in the double buffer, and T00PWM (T00REG) is not updated immediately.
T00PWM (T00REG) compares the previous set value with the up counter value. When an
INTTC00 interrupt request is generated, the double buffer set value is stored in T00PWM
(T00REG). Subsequently, the match detection is executed using a new set value.
last set value) is read out, not the T00PWM (T00REG) value (the currently effective value).
set value is immediately stored in both the double buffer and T00PWM (T00REG).
set value is immediately stored in T00PWM (T00REG). Subsequently, the match detection is
executed using a new set value. If the value set to T00PWM (T00REG) is smaller than the up
counter value, the PPG0 pin is not reversed until the up counter overflows and a match detection
is executed using a new set value. If the value set to T00PWM (T00REG) is equal to the up counter
value, the match detection is executed immediately after data is written into T00PWM (T00REG).
Therefore, the timing of changing the PPG0 pin may not be an integral multiple of the source clock
(Figure 14-10). If these are problems, enable the double buffer.
set value is immediately stored in T00PWM (T00REG).
When a write instruction is executed on T00PWM (T00REG) during the timer operation, the
When a read instruction is executed on T00PWM (T00REG), the value in the double buffer (the
When a write instruction is executed on T00PWM (T00REG) while the timer is stopped, the
When a write instruction is executed on T00PWM (T00REG) during the timer operation, the
When a write instruction is executed on T00PWM (T00REG) while the timer is stopped, the
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