TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 251

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

RA001
16.12
16.12.1
RXD0 pin input
UART0SR<PERR>
INTRXD0 interrupt request
Reading of UART0SR
Reading of RD0BUF
RD0BUF
RXD0 pin input
UART0SR<PERR>
INTRXD0 interrupt request
Reading of UART0SR
Reading of RD0BUF
RD0BUF
UART0SR<PERR> is set to "1". At this time, an INTRXD0 interrupt request is generated.
RD0BUF is read subsequently. (The RD0BUF read value becomes undefined.)
when RD0BUF is read subsequently. In this case, UART0SR<PERR> will be cleared to "0" when UART0SR is
read again and RD0BUF is read.
Status Flag
When the parity determined using the receive data bits differs from the received parity bit, the parity error flag
If UART0SR<PERR> is "1" when UART0SR is read, UART0SR<PERR> will be cleared to "0" when
If UART0SR<PERR> is set to "1" after UART0SR is read, UART0SR<PERR> will not be cleared to "0"
Parity error
Start Bit0
Start Bit0
Figure 16-10 Occurrence of Parity Error
Bit1
Bit1
Bit2
Bit2
Bit3
Bit3
Bit4
Bit4
Page 235
Bit5
Bit5
Bit6
Bit6
Bit7 Parity Stop
Bit7 Parity Stop
Indeterminate
Indeterminate
Data reading
Not cleared
Data reading
PERR is cleared to “0”
when RD0BUF
is read after reading PERR=“1”.
Data reading
PERR is cleared to “0”
when RD0BUF
is read after reading PERR=“1”.
TMP89FS60