TMP89xy60UG/FG Toshiba, TMP89xy60UG/FG Datasheet - Page 30

• Manufacturer Part Number: TMP89xy60UG/FG
• Manufacturer: Toshiba

Specifications of TMP89xy60UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 32/60
• Ram Size: 3K
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: -
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: Y
• Number Of I/o Ports: 58
• Power Supply (v): 4.3 to 5.5

2.2
Memory space
RB000
Flash memory control register 1
Flash memory control register 2
(0x0FD0)
(0x0FD1)
FLSCR1
FLSCR2
2.2.2.3
2.2.2.4
Note:The flash memory control register 1 has a double-buffer structure comprised of the register FLSCR1 and a shift
CLR_RAM:
register. Writing "0xD5" to the register FLSCR2 allows a register setting to be reflected and take effect in the shift
register. This means that a register setting value does not take effect until "0xD5" is written to the register FLSCR2.
The value of the shift register can be checked by reading the register FLSCRM.
Example: RAM initialization program
0x17FF in the code area and to 0x1000 to 0x17FF in the data area. Flash memory can be easily programmed
by using the API (Application Programming Interface) contained in the BOOTROM.
Read/Write
BAREA
Read/Write
CR1EN
Bit Symbol
Bit Symbol
After reset
After reset
The BOOTROM is not mapped in the code area or the data area after reset release.
The Flash is mapped to 0x1000 to 0xFFFF in the data area after reset release.
BOOTROM
Flash
Setting FLSCR1<BAREA> to "1" and writing 0xD5 to FLSCR2 maps the BOOTROM to 0x1000 to
Note1: Only the first 2 Kbytes of the BOOTROM are mapped in the memory map, except in the serial PROM
LD
LD
LD
LD
INC
DEC
J
Specifies mapping of the BOOT-
ROM in the code and data areas
FLSCR1 register
enable/disable control
mode.
HL, RAM_TOP_ADDRESS
A, 0x00
BC, BYTE_OF_CLEAR_BYTES
(HL), A
HL
BC
F, CLR_RAM
7
0
7
*
(FLSMD)
R/W
6
1
6
*
5
0
5
Others
*
Page 14
0 :
1 :
0xD5
The BOOTROM is not mapped to 0x1000 to 0x17FF in the code area and
to 0x1000 to 0x17FF in the data area.
The BOOTROM is mapped to 0x1000 to 0x17FF in the code area and to
0x1000 to 0x17FF in the data area.
Enable a change in the FLSCR1 setting
Reserved
BAREA
R/W
;Head of address of the RAM to be initialized
;Initialization data
;Number of bytes of RAM to be initialized -1
;Initialization of the RAM
;Initialization address increment
;Have all the RAMs been initialized?
4
0
4
*
CR1EN
W
3
0
3
*
(FAREA)
R/W
2
0
2
*
1
0
1
*
(ROMSEL)
TMP89FS60
R/W
0
0
0
*